All digital transistor high gain operational amplifier using positive feedback technique

Amourah, M.M.; Geiger, R.L.

doi:10.1109/iscas.2002.1009937

Cited by 18 publications

(9 citation statements)

References 5 publications

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“…The amplifier circuit considered here ( Fig. 2a) is similar to the first one proposed in the literature on positive-feedback amplifiers (see [23,Fig. 1a]).…”

Section: Analysis Of the "Positive-feedback" Amplifiermentioning

confidence: 99%

“…The problem is inherently related to the compensation technique and it was also found to affect NDR GFETs [21]. In the literature on positive-feedback amplifiers, some more complex versions of the amplifier have been proposed to reduce non-linearity [23].…”

Section: Non-linearitymentioning

confidence: 99%

“…In the context of standard CMOS analog circuit design, a technique based on a similar concept of conductance cancellation (named "positive-feedback" or "negative conductance" technique) has been proposed to enhance the gain and gain-bandwidthproduct (GBW) of amplifiers [22][23][24]. In this case, the output conductance is positive and a feedback from the output node is used to generate a negative load conductance that compensates its value, thereby achieving high gains.…”

Section: Introductionmentioning

confidence: 99%

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Boosting the voltage gain of graphene FETs through a differential amplifier scheme with positive feedback

Grassi

Gnudi

Lecce

et al. 2014

Solid-State Electronics

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We study a possible circuit solution to overcome the problem of low voltage gain of short-channel graphene FETs. The circuit consists of a fully differential amplifier with a load made of a cross-coupled transistor pair. Starting from the device characteristics obtained from self-consistent ballistic quantum transport simulations, we explore the circuit parameter space and evaluate the amplifier performance in terms of dc voltage gain and voltage gain bandwidth. We show that the dc gain can be effectively improved by the negative differential resistance provided by the cross-coupled pair. Contact resistance is the main obstacle to achieving gain bandwidth products in the terahertz range.Limitations of the proposed amplifier are identified with its poor linearity and relatively large Miller capacitance.

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“…The amplifier circuit considered here ( Fig. 2a) is similar to the first one proposed in the literature on positive-feedback amplifiers (see [23,Fig. 1a]).…”

Section: Analysis Of the "Positive-feedback" Amplifiermentioning

confidence: 99%

Section: Non-linearitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Boosting the voltage gain of graphene FETs through a differential amplifier scheme with positive feedback

Grassi

Gnudi

Lecce

et al. 2014

Solid-State Electronics

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show abstract

“…On the other hand, instead of using single-stage topologies, engineers tend to use multi-stages to achieve higher DC gains. As an alternative, positive feedback [3], feed-forward [4] or regulated feed-forward [5] techniques can be applied to single-stage amplifiers. However, the majority of these techniques still lean on cascode structures.…”

Section: Introductionmentioning

confidence: 99%

A voltage-combiners-biased amplifier with enhanced gain and speed using current starving

Póvoa

Lourenço

Horta

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this paper, the current starving technique is applied to a voltage-combiners-biased symmetrical CMOS Operational Transconductance Amplifier (OTA). The proposed topology upgrade enhances the gain of the conventional topology, improves the settling time by means of enhancing its gainbandwidth product and highly improves its energy efficiency. Simulation results of a properly optimized circuit, using AIDA-C, a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, demonstrate that a DC gain above 60 dB can be achieved together with a high energy efficiency (a figure-ofmerit of 2200 MHz×pF/mA has been reached). The circuit was designed using a standard 130 nm CMOS technology and drains less than 0.5 mA from a 3.3 V power supply.

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“…Comparatively, the g ds cancellation method has the potential to provide high DC gain enhancement for amplifiers without degrading their high-frequency performances. However, the currently proposed g ds cancellation methods [2][3][4][5][6][7] are not widely adopted because of various drawbacks. For example, some approaches [2,3] heavily rely on the precise matching between the transistor's transconductance and output conductance, which is highly impractical over process and wide temperature variation.…”

mentioning

confidence: 99%

Power‐efficient, PVT robust conductance cancellation method for gain enhancement

Huang

Chen

2013

Electron. lett.

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A power-efficient, process, voltage and temperature (PVT) robust g ds cancellation method for gain enhancement is proposed. The method generates a negative conductance, which matches and cancels the positive conductance. This makes the g ds cancellation method effective over process and wide temperature variation without the aid of external calibration or a tuning circuit. The method senses signals from cascode nodes instead of output nodes, making the method insensitive to output voltage swing. The simulation results of an example implementation in IBM 0.13 µm process show at least 22 dB DC gain enhancement over all process corners and temperatures ranging from − 20 to 80°C, with less than 9% power consumption overhead.

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All digital transistor high gain operational amplifier using positive feedback technique

Cited by 18 publications

References 5 publications

Boosting the voltage gain of graphene FETs through a differential amplifier scheme with positive feedback

Boosting the voltage gain of graphene FETs through a differential amplifier scheme with positive feedback

A voltage-combiners-biased amplifier with enhanced gain and speed using current starving

Power‐efficient, PVT robust conductance cancellation method for gain enhancement

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