ADRES &amp; DRESC: Architecture and Compiler for Coarse-Grain Reconfigurable Processors

Mei, Bingfeng; Berekovic, Mladen; Mignolet, J.-Y.

doi:10.1007/978-1-4020-6505-7_6

Cited by 26 publications

(31 citation statements)

References 21 publications

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“…Most of existing reconfigurable SoCs (e.g. [5,32,33,35] and [29]) are based on sharedbus or crossbar interconnection infrastructures. However, some NoC-based reconfigurable SoCs (e.g.…”

Section: Architecture Of Reconfigurable Socsmentioning

confidence: 99%

“…), some adopt CGRA (e.g. MorphoSys [66], PACT XPP-III [67], ADRES [35], and REMUS [68] etc. ), while others incorporate both (e.g.…”

Section: Reconfigurable Processing Farbicsmentioning

confidence: 99%

“…The CGRA can be a domain-specific system (e.g. ADRES [35], and REMUS [68] etc.) or an application-specific system (e.g.…”

Section: Reconfigurable Processing Farbicsmentioning

confidence: 99%

“…By contrast, low-level simulators are required when Figure 5. ADRES architecture template [35] the purpose of simulation is to aim at evaluating the performance or power consumption of NoC proposals. High-level simulators are usually written in either C ++ language, such as VNOC, Booksim, and TOPAZ, etc.…”

Section: Simulatorsmentioning

confidence: 99%

“…ADRES [35] (Architecture for Dynamically Reconfigurable Embedded System) is a reconfigurable system template ( Figure 5), which tightly couples a VLIW processor and a coarse-grained reconfigurable matrix. The VLIW processor and the coarse-grained reconfigurable matrix are integrated into a single architecture but with two virtual functional views.…”

Section: Adresmentioning

confidence: 99%

See 4 more Smart Citations

A Survey on Reconfigurable System-on-Chips

Nguyen

Le-Van

Tran

2018

REV J. Electron. Commun.

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Abstract-The requirements for high performance and low power consumption are becoming more and more inevitable when designing modern embedded systems, especially for the next generation of multi-mode multimedia or communication standards. Ultra large-scale integration reconfigurable System-on-Chips (SoCs) have been proposed to achieve not only better performance and lower energy consumption but also higher flexibility and versatility in comparison with the conventional architectures. The unique characteristic of such systems is the integration of many types of heterogeneous reconfigurable processing fabrics based on a Network-on-Chip. This paper analyzes and emphasizes the key research trends of reconfigurable System-on-Chips (SoCs). Firstly, the emerging hardware architecture of SoCs is highlighted. Afterwards, the key issues of designing reconfigurable SoCs are discussed, with the focus on the challenges when designing reconfigurable hardware fabrics and reconfigurable Network-on-Chips. Finally, some state-of-the-art reconfigurable SoCs are briefly discussed.

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“…Most of existing reconfigurable SoCs (e.g. [5,32,33,35] and [29]) are based on sharedbus or crossbar interconnection infrastructures. However, some NoC-based reconfigurable SoCs (e.g.…”

Section: Architecture Of Reconfigurable Socsmentioning

confidence: 99%

“…), some adopt CGRA (e.g. MorphoSys [66], PACT XPP-III [67], ADRES [35], and REMUS [68] etc. ), while others incorporate both (e.g.…”

Section: Reconfigurable Processing Farbicsmentioning

confidence: 99%

“…The CGRA can be a domain-specific system (e.g. ADRES [35], and REMUS [68] etc.) or an application-specific system (e.g.…”

Section: Reconfigurable Processing Farbicsmentioning

confidence: 99%

Section: Simulatorsmentioning

confidence: 99%

Section: Adresmentioning

confidence: 99%