Addressing End-to-End Memory Access Latency in NoC-Based Multicores

Sharifi, Akbar; Kültürsay, Emre; Kandemir, Mahmut; Das, Chita R.

doi:10.1109/micro.2012.35

Cited by 34 publications

(9 citation statements)

References 28 publications

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“…So, these metrics are not very accurate for ranking application criticality. Recently proposed network scheduling schemes in [18] aim to bring uniformity in network latencies and main memory bank utilization by applying separate rules to request and response packets. However, the techniques are application-oblivious and can lead to increased delays in the system while trying to equalize packet latencies.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

NoC Scheduling for Improved Application-Aware and Memory-Aware Transfers in Multi-core Systems

Pimpalkhute

Pasricha

2014

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

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In a multi-core environment with several applications executing in parallel, system performance is significantly impacted by network and memory performance. The manner in which network packets and off-chip memory bound packets are handled determines end-to-end latencies across the network and memory. Several techniques have been proposed in the past that schedule packets in an application-aware manner or memory requests in a DRAM row/bank locality aware manner. In this paper, we propose a holistic framework that integrates novel scheduling techniques for both network and memory accesses and operates cohesively in an application-aware and memory-aware manner to optimize overall system performance. Experimental results indicate that our technique performs well for systems with high speed memories, improving system throughput by up to 16.7%, memory latency by up to 11%, and energy consumption by up to 10% compared to prior work on NoC packet scheduling.

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Section: Related Workmentioning

confidence: 99%

“…Some of the standard and previously proposed anti-starvation strategies are discussed below. In [3][4] [18], time-based (TB) batching is employed to enable fairness among application packets. In time-based batching, a packet is tagged with a batch id that is a function of the time when it is injected into the NoC.…”

Section: Fairness Issues In Packet Schedulingmentioning

confidence: 99%

NoC Scheduling for Improved Application-Aware and Memory-Aware Transfers in Multi-core Systems

Pimpalkhute

Pasricha

2014

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

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“…Memory-centric NoC architectures with real chip implementations are studied in [35]. Recent work [36] tried to reduce end-to-end memory access latency in NoC-based multicore system by prioritizing memory response packets and messages destined for idle memory banks. Memory placement mechanisms in NUMA systems such as page migration [37][38][39], interleaving [2] and replication [2,40] have been studied for decades.…”

Section: Optimization Of Memory Access Trafficmentioning

confidence: 99%

Optimizing memory access traffic via runtime thread migration for on-chip distributed memory systems

Chen

Wang

et al. 2014

J Supercomput

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On-chip distributed memory system has become an attractive solution for massive parallel memory accesses found in future many-core processors. However, increasing number of on-chip cores and memory controllers inevitably introduce many remote memory accesses, which generate a large amount of on-chip traffic and put great pressure on the interconnection. This paper tries to optimize on-chip memory access traffic via runtime thread migration. We first analyze memory access behaviors in multi-threaded applications and find that the memory access targets and volumes are similar during short periods, which makes runtime prediction feasible. But the memory access targets exhibit great mobility during long periods, motivating us to dynamically move threads towards the data. Based on these observations, we propose a novel low-cost and distributed thread migration algorithm which adjusts thread placement in chains based on benefit estimation. We present details of the workflow, including the trigger and arbitration of migration requests and the procedures to determine the migration chains. Simulation results show that our algorithm achieves system performance speedup of 11.5 % and reduces average memory access latency by 11.0 %. It can find a few but effective thread migrations to optimize on-chip memory access traffic with acceptable hardware and runtime overheads.

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“…Different from them, we focus on balancing the latencies amongst the on-chip memory accesses. In [11], Sharifi addressed balancing latencies of on-chip memory accesses by prioritizing memory response packets such that, in a given period of time,packets that experience higher latencies than the average packet latency of that application are expedited. However, they divided a whole memory access into two parts: outward trip for memory request (read or write) and return trip for memory response (read data or write acknowledgement) and treated them separately.…”

Section: Introduction Motivation and Related Workmentioning

confidence: 99%

Round-trip latency prediction for memory access fairness in mesh-based many-core architectures

Chen

Zhao

et al. 2014

IEICE Electron. Express

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In mesh-based many-core architectures, processor cores and memories reside in different locations (center, corner, edge, etc.), therefore memory accesses behave differently due to their different communication distances. The latency difference leads to unfair memory access and some memory accesses with very high latencies, degrading the system performance. However, improving one memory access's latency can worsen the latency of another since memory accesses contend in the network. Therefore, the goal should focus on memory access fairness through balancing the latencies of memory accesses while ensuring a low average latency. In the paper, we address the goal by proposing to predict the round-trip latencies of memory access related packets and use the predicted round-trip latencies to prioritize the packets. The router supporting fair memory access is designed and its hardware cost is given. Experiments are carried out with a variety of network sizes and packet injection rates and prove that our approach outperforms the classic round-robin arbitration in terms of average latency and LSD 1 . In the experiments, the maximum improvement of the average latency and the LSD are 16% and 48% respectively. Keywords: round-trip, fair memory access, mesh, many-core Classification: Integrated circuits

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Addressing End-to-End Memory Access Latency in NoC-Based Multicores

Cited by 34 publications

References 28 publications

NoC Scheduling for Improved Application-Aware and Memory-Aware Transfers in Multi-core Systems

NoC Scheduling for Improved Application-Aware and Memory-Aware Transfers in Multi-core Systems

Optimizing memory access traffic via runtime thread migration for on-chip distributed memory systems

Round-trip latency prediction for memory access fairness in mesh-based many-core architectures

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