Additivity of capacitive and inductive coupling in submicronic interconnects

Abstract

Abstract-Constant evolution in integrated circuit technology has led to an increase in the switching speed of the digital chip. As a result, there is a growing interest in the inductance associated with signal lines. Inductive coupling effects on interconnects is an emerging concern in high performance digital integrated circuits. Based on an RLC transmission line model, associated to each propagation mode, a new crosstalk noise model is proposed to evaluate both the capacitive and the inductive coupling. The additivity of the coupling is shown and validated with several simulations.

Analytical crosstalk noise characteristics

“…We will now compare these results with crosstalk voltages characteristics simulated from the reference distributed coupled-line system. Remark that the reference and the equivalent models are described in our previous works [6] [7]. For the electrical simulations, we use the electrical parameters we have determined for a 1GHz frequency on an upper level typical interconnect geometry.…”

“…In [7], we have shown that the crosstalk resulting to the total coupling (capacitive + inductive) could be written as the sum of the coupling effects. In Laplace domain, crosstalk voltage can be written as: …”

Multi-aggressor capacitive and inductive coupling noise modeling and mitigation

“…According to [10], capacitive and inductive coupling noise is additive under the low loss approximation, () however that the low loss approximation cannot always be assumed in modern integrated circuits. Therefore, additivity of the two noise sources cannot be assumed in modern integrated circuits.…”

“…Therefore, additivity of the two noise sources cannot be assumed in modern integrated circuits. By performing an analysis similar to [10], those regimes where additivity of capacitive and inductive coupling can be assumed, as illustrated in Fig. 3 for a two coupled line system, are established.…”

“…Another case where (2.4) is satisfied is the low loss approximation [4], [10]. This approximation, however, is not always appropriate in modern semiconductor processes.…”