Activation of Logic Encrypted Chips: Pre-Test or Post-Test?

Yasin, Muhammad; Saeed, Samah Mohamed; Rajendran, Jeyavijayan; Sinanoglu, Ozgur

doi:10.3850/9783981537079_0687

Cited by 56 publications

(19 citation statements)

References 14 publications

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“…Test generation and application can thus be performed based on dummy logic locking keys. The flow therefore shows post-test activation of chips, as this is the most secure strategy [18].…”

Section: The Sat Attackmentioning

confidence: 99%

ScanSAT: Unlocking Static and Dynamic Scan Obfuscation

Alrahis

Yasin

Limaye

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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While financially advantageous, outsourcing key steps, such as testing, to potentially untrusted Outsourced Assembly and Test (OSAT) companies may pose a risk of compromising on-chip assets. Obfuscation of scan chains is a technique that hides the actual scan data from the untrusted testers; logic inserted between the scan cells, driven by a secret key, hides the transformation functions that map the scan-in stimulus (scan-out response) and the delivered scan pattern (captured response). While static scan obfuscation utilizes the same secret key, and thus, the same secret transformation functions throughout the lifetime of the chip, dynamic scan obfuscation updates the key periodically. In this paper, we propose ScanSAT: an attack that transforms a scan obfuscated circuit to its logic-locked version and applies the Boolean satisfiability (SAT) based attack, thereby extracting the secret key. We implement our attack, apply on representative scan obfuscation techniques, and show that ScanSAT can break both static and dynamic scan obfuscation schemes with 100% success rate. Moreover, ScanSAT is effective even for large key sizes and in the presence of scan compression.

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“…Test generation and application can thus be performed based on dummy logic locking keys. The flow therefore shows post-test activation of chips, as this is the most secure strategy [18].…”

Section: The Sat Attackmentioning

confidence: 99%

ScanSAT: Unlocking Static and Dynamic Scan Obfuscation

Alrahis

Yasin

Limaye

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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“…Test patterns for such test are generated assuming that key inputs are controllable; thus, the correct K L value is not required. This procedure is shown to provide maximum fault coverage while preventing attackers from retrieving K L by analysing test patterns [24].…”

Section: B Testability Analysismentioning

confidence: 99%

A Secure Scan Controller for Protecting Logic Locking

Nguyen

Valea

Flottes

et al. 2020

2020 IEEE 26th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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The globalized supply chain in the Integrated Circuit (IC) industry raises several security concerns such as overproduction, IP piracy and Hardware Trojan insertion. Logic locking has emerged as a potential countermeasure to address these issues. However, its efficiency is challenged by various attacks, especially oracle-guided attacks based on Boolean Satisfiability (SAT) solvers. These attacks rely on the possibility for an attacker to control and observe in the field the internal state of a functional IC, which acts as an oracle. This ability to control/observe the IC states is offered by scan chains, typically used for IC production testing. In this paper, we propose a method, complementary to logic locking, to prevent such attacks. This method introduces a scan chain controller with a key-based authentication mechanism, in order to prevent unauthorized access to the scan chains once the IC is deployed in the field. The solution can be coupled with any logic locking technique at the cost of negligible area overhead. Furthermore, it is secure against state-of-the-art attacks and supports full testing.

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“…Note that these threats arise due to the globalized and distributed nature of modern IC supply chains, which span across many parties and countries [4]. Over the last decade, a multitude of protection schemes have been Logic Locking ✓/✓ ✓ (see also [5]) ✓ Layout Camouflaging ✗/✗ (✓/✗ [6], ✓/✓ [7]) ✗ (✓ [7]) ✓ Split Manufacturing ✓/✗ (✗/✓ [8]) ✗ ✗ (✓ [9, 10]) proposed (and selectively already implemented in silicon), which can be broadly classified into logic locking, layout camouflaging, and split manufacturing. All these techniques seek to protect the hardware from different attackers, as summarized in Table 1.…”

Section: Introductionmentioning

confidence: 99%

Protect Your Chip Design Intellectual Property

Knechtel

Patnaik

Sinanoglu

2019

Proceedings of the International Conference on Omni-Layer Intelligent Systems

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The increasing cost of integrated circuit (IC) fabrication has driven most companies to "go fabless" over time. The corresponding outsourcing trend gave rise to various attack vectors, e.g., illegal overproduction of ICs, piracy of the design intellectual property (IP), or insertion of hardware Trojans (HTs). These attacks are possibly conducted by untrusted entities residing all over the supply chain, ranging from untrusted foundries, test facilities, even to end-users. To overcome this multitude of threats, various techniques have been proposed over the past decade. In this paper, we review the landscape of IP protection techniques, which can be classified into logic locking, layout camouflaging, and split manufacturing. We discuss the history of these techniques, followed by state-of-the-art advancements, relevant limitations, and scope for future work. CCS CONCEPTS• Security and privacy → Security in hardware;

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Activation of Logic Encrypted Chips: Pre-Test or Post-Test?

Cited by 56 publications

References 14 publications

ScanSAT: Unlocking Static and Dynamic Scan Obfuscation

ScanSAT: Unlocking Static and Dynamic Scan Obfuscation

A Secure Scan Controller for Protecting Logic Locking

Protect Your Chip Design Intellectual Property

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