AC-coupling strategy for high-speed transceivers of 10Gbps and beyond

Abstract

AC coupling in a transmission link is preferred and often required for the functioning of high speed transceivers. But at data rate of 10Gbps and beyond, both the external AC coupling and the conventional on-chip AC coupling approaches bring in heavy burden that pushes to the fundamental limits and are difficult to afford. This paper examines the AC-coupling methods for multi-Gb/s transceivers, and points out the impairments in the existing implementations. A hybrid structure offering both the signal-bump and the AC-capacitor functions under the stringent return-loss requirements of a 10Gb/s+ I/O is proposed and implemented in 65nm standard CMOS. A sizeable 5.1pF AC capacitor is measured with ultra low parasitic expense ratio of less than 120fF.I.

A Capacitively Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver

“…This minimizes channel loss and is well suited for AC coupled interfaces. AC connections can increase I/O density and chances for rework [13] [17], which eases manufacturing concerns and maximizes freedom for commercialization and intellectual property reuse [18]. However, specialized circuitry is needed in order to take full advantage of these techniques and meet data throughput demand.…”

“…On-board capacitors have become a limiting factor in that they require VIA stubs, which create complex channel responses due to input stage impedance discontinuities, loss, dispersion and reflections [10]. The addition of just two mounting VIA stubs, loss can surpass 3 dB [18]. In addition, board technology miniaturization and cost have not kept pace with very large scale integration (VLSI) technology scaling.…”