A VLSI design concept for parallel iterative algorithms

Abstract

Abstract. Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array) in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors) usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified µ-rotation CORDIC architecture.

An Efficient VLSI Architecture for FastICA by Using the Algebraic Jacobi Method for EVD

“…CORDIC algorithm is a hardware-friendly iterative technique developed for implementing the elementary functions of mathematics by using only add and shift operations [26]. It can be used for computing sine, cosine, and arctangent in EVD by the EJM [32], [33]. If N is the total number of CORDIC iterations, which usually is equal to the wordlength of the hardware architecture, then mathematically CORDIC can be described using the equations from ( 23) to (26), where = 0, 1, 2, … .…”

“…ASIC-based implementations of FastICA can be optimized with respect to speed or power [32] and hardware complexity can be neglected to some extent because even a complex design can be optimized for power by carefully selecting technology node and operating voltage as in [11], [13]. ASICbased designs are useful at the commercialization stage.…”

Bit parallel - iterative circuit for robotic application

“…Based on equation (2), the sum circuits need three inputs. The A⊕B circuit is directly connected to input 'C' which is developed according to equation (1). In order to avoid an increasing number of transistors due to addition of third input, XOR gate output is fed through NOT gate from differential node to C andC inputs of full adder, thereby reducing the number of transistors to six in sum circuit.…”

“…The CORDIC algorithm is very well suited for VLSI implementation due to simplicity of involved operations [1] which can be designed for scale factor correction and accuracy issues with respect to fixed word-bit implementation. These corrections of word-bit circuit could be implementing by pass transistor logic, which is identified and corrected the fault according to hardware description.…”