DOI: 10.1109/isscc.1983.1156460
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Abstract: THIS PAPER WILL DESCRIBE a Memory Management Unit (MMU)" for a 32b CPU**, implemented on a 270-square mil die utilizing 3.5p NMOS technology. The chip contains approximately 20,000 transistors and is housed in a 48-pin dual-in-line package. A photomicrograph of the chip is shown in Figure 1.The main function of the device is to translate memory addresses which the CPU attempts t o access. While doing so it checks access rights ana validity (i.e., the existence of the desired location in main memory), supporti…

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