A very low area ADC for 3-D stacked CMOS image processing system

Kiyoyama, K.; Lee, K.-W.; Fukushima, T.; Naganuma, H.; Kobayashi, H.; Tanaka, Tetsu; Koyanagi, Mitsumasa

doi:10.1109/3dic.2012.6262958

Cited by 15 publications

(11 citation statements)

References 10 publications

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“…The maximum N ADC value is set to the number of columns at pyramid Level 0, since image sensors with one ADC per column are commonly found [63]. Although stacking technologies allow for the integration of one ADC per pixel [23], this is still an upcoming technology with high fabrication costs.…”

Section: Time Comparison Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Gaussian Pyramid: Comparative Analysis of Hardware Architectures

Oliveira

Gomes

Fernández-Berni

et al. 2017

IEEE Trans. Circuits Syst. I

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Abstract-The paper addresses a comparison of architectures for hardware implementation of Gaussian image pyramids. Main differences between architectural choices are in the sensor frontend. One side is for architectures consisting of a conventional sensor that delivers digital images and which is followed by digital processors. The other side is for architectures employing a non-conventional sensor with per-pixel embedded pre-processing structures for Gaussian spatial filtering. This later choice belongs to the general category of "artificial retina" sensors which have been for long claimed as potentially advantageous for enhancing throughput and reducing energy consumption of vision systems. These advantages are very important in the internet of things context, where imaging systems are constantly exchanging information. The paper attempts to quantify these potential advantages within a design space in which the degrees of freedom are the number and type of ADCs (single-slope, SAR, cyclic, Σ∆ and pipeline), and the number of digital processors. Results show that speed and energy advantages of pre-processing sensors are not granted by default and are only realized through proper architectural design. The methodology presented for the comparison between focal-plane and digital approaches is a useful tool for imager design, allowing for the assessment of focal-plane processing advantages.

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Section: Time Comparison Resultsmentioning

confidence: 99%

“…To compare ADC types and find the appropriate clock period in each case, we use reported imagers in which the performance figures of the embedded ADCs are included [23]- [58]. ADCs have already been compared by different authors [22], [59].…”

Section: Adc Architectures Comparisonmentioning

confidence: 99%

Gaussian Pyramid: Comparative Analysis of Hardware Architectures

Oliveira

Gomes

Fernández-Berni

et al. 2017

IEEE Trans. Circuits Syst. I

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“…The CMOS image sensor (CIS) layer and CDS layer were fabricated using a standard 0.18-m CMOS image sensor and mixed signal technology, respectively. These circuit designs for the 3-D stacked CMOS image sensor with blockparallel image signal processing circuit had been presented in [16]. In our 3-D stacked CMOS image sensor, FPN of pixel output is removed by analog CDS circuit, and in addition digital CDS is used to eliminate the FPNs (i.e.…”

Section: System Overviewmentioning

confidence: 99%

“…In recent years, various prior researches have described that 3-D integrations provide new opportunities for high speed and high resolution CMOS image sensor design [12][13]. To realize a CMOS image sensor having high speed, high sensitivity, and high resolution with digital data readout, we have proposed a block-parallel image processing system with 3-D stacked structure [1][2][3] [14][15][16][17]. In this paper, we describe a block-parallel ADC with hierarchical double correlated double sampling for 3-D stacked structure to achieve a high frame rate with digital data readout in a CMOS image sensor.…”

Section: Introductionmentioning

confidence: 99%

A block-parallel ADC with digital noise cancelling for 3-D stacked CMOS image sensor

Kiyoyama

Sato

Hashimoto

et al. 2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

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An ADC design with a hierarchical double correlated double sampling for a three-dimensional (3-D) stacked CMOS image sensor is presented in this paper. To realize high speed, high resolution, and high sensitivity, we have proposed a blockparallel signal processing with 3-D structure. The block-parallel analog signal processing elements which compose CMOS image sensor, correlated double sampling (CDS) with programmable gain amplifier (PGA) array, and analog-to-digital converter (ADC) array. Spatial noise is the main contributor of image distortion in CMOS image sensor. Fixed pattern noise (FPN) does not change with time, and causes fixed distortion pattern on the image, hence FPN correction is especially challenging in the high speed CMOS image sensor. In the proposed sensor system, FPN of pixel output is removed by analog CDS. The digital CDS proposed in this paper is used to eliminate FPN caused by the device variation of analog circuits. The proposed ADC was designed with 90-nm CMOS technology. The proposed ADC with digital CDS occupies a very small circuit area of 160×160 m 2 . The block-parallel ADC performance is characterized through differential nonlinearity (DNL) and integral nonlinearity (INL) measurements. The DNL is within -1.49/+1.89 LSB, and the INL is -1.92/+2.44 LSB, respectively. FPN is reduced to the range of ±1LSB by using proposed hierarchical double CDS function.

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“…Several different types of 3D stacked image sensors have recently been reported [12][13][14][15][16][17][18][19][20] by using through-silicon vias (TSVs) and microbump technology. However, a TSV or microbump was shared by multiple pixels, and pixel-parallel signal processing was not realized in such sensors, because the diameter of the TSVs or bumps was larger than the pixel size of a few micrometers or less.…”

Section: Introductionmentioning

confidence: 99%

Three-dimensional integrated CMOS image sensors with pixel-parallel A/D converters fabricated by direct bonding of SOI layers

Goto¹,

Hagiwara²,

Iguchi³

et al. 2014

2014 IEEE International Electron Devices Meeting

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We report the first demonstration of three-dimensional (3D) integrated CMOS image sensors with pixel-parallel A/D converters (ADCs). Photodiode (PD) and inverter layers were directly bonded with the damascened Au electrodes to provide each pixel with in-pixel A/D conversion. We designed ADC with a pulse frequency output and fabricated a prototype sensor with 64 pixels. The developed sensor successfully captured video images and confirmed excellent linearity with a wide dynamic range of more than 80 dB, which showed feasibility of pixel-level 3D integration for high-performance CMOS image sensors.

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A very low area ADC for 3-D stacked CMOS image processing system

Cited by 15 publications

References 10 publications

Gaussian Pyramid: Comparative Analysis of Hardware Architectures

Gaussian Pyramid: Comparative Analysis of Hardware Architectures

A block-parallel ADC with digital noise cancelling for 3-D stacked CMOS image sensor

Three-dimensional integrated CMOS image sensors with pixel-parallel A/D converters fabricated by direct bonding of SOI layers

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