A Vertically Integrated Pixel Readout Device for the Vertex Detector at the International Linear Collider

Abstract

Abstract-3D-Integrated Circuit technology enables higher densities of electronic circuitry per unit area without the use of nanoscale processes. It is advantageous for mixed mode design with precise analog circuitry because processes with conservative feature sizes typically present lower process dispersions and tolerate higher power supply voltages, resulting in larger separation of a signal from the noise floor. Heterogeneous wafers (different foundries or different process families) may be combined with some 3D integration methods, leading to the optimization of each tier in the 3D stack. Tracking and vertexing in future High-Energy Physics (HEP) experiments involves construction of detectors composed of up to a few billions of channels. Readout electronics must record the position and time of each measurement with the highest achievable precision. This paper reviews a prototype of the first 3D readout chip for HEP, designed for a vertex detector at the International Linear Collider. The prototype features 20×20 μm 2 pixels, laid out in an array of 64×64 elements and was fabricated in a 3-tier 0.18 μm Fully Depleted SOI CMOS process at MIT-Lincoln Laboratory. The tests showed correct functional operation of the structure. The chip performs a zero-suppressed readout. Successive submissions are planned in a commercial 3D bulk 0.13 μm CMOS process to overcome some of the disadvantages of an FDSOI process.

The International Linear Collider Technical Design Report - Volume 4: Detectors

“…Here also arises the question of currency exchange rates, which change often unstably, in estimating the total cost in one particular currency. The number of participating institutions and their counties 19 The detector top node in the ILC-EDMS and the details for the two detectors SID and ILD will be very many, exceeding those of accelerator participation, and the unstable exchange rates requires careful handling in producing an total cost estimation, while in practice they will not cause a serious problem at the time of construction because most components will be provided by in-kind contribution. The HEP community has rich experience for building large collider detectors in big international collaborations handling these matters smoothly.…”

“…In this manner, the poor hadronic energy resolution a ects only about 10% of the energy in the jet and a jet energy resolution of about 0. 19/  E(GeV) would be ideally obtained. In practice, this level of performance cannot be achieved as it is impossible to perfectly associate all energy deposits with the correct particles.…”

“…The Vertically Integrated Pixel (VIP) chip was conceived as a demonstration readout chip for the ILC vertex detector. The first version of the chip (VIP2a) was a three-tier device produced at MIT Lincoln Laboratory using a fully depleted SOI process [19]. A major success was that all of the interconnections between the circuit layers worked.…”

“…The Vertically Integrated Pixel (VIP) ASIC was conceived of as a demonstration readout chip for the ILC vertex detector [82]. The Lincoln Laboratory process has the advantage of very well-established wafer bonding and thinning, but the fully depleted SOI process is not well suited for analog applications and has larger feature size than advanced commercial processes.…”

Vertically integrated circuits at fermilab

“…The fabrication of the first 3D chip, called Vertically Integrated Pixel (VIP1) designed at Fermilab, was realized wit the 3D-IC MIT-LL process using the via last approach [21]. The VIP1 chip is a demonstrator serving as proof of the 3D-IC principle for HEP.…”