A SystemC Virtual Prototyping based Methodology for Multi-Standard SoC Functional Verification

Abstract

This paper describes a functional verification methodology for multi-standard wireless Systems-on-Chip (SoC) based on SystemC Virtual Prototyping (VP). The proposed semiautomatic pin-accurate RF VP generation method reduces huge handcrafting work to abstract circuitry into the eventdriven simulation domain with satisfactory accuracy, while enabling the flexibility to choose different abstraction levels. A seamless transition between various signal abstractions is enabled by operator overload, e.g. passband and equivalent baseband in order to minimize simulation time according to test cases. This methodology is demonstrated for a low power RF transceiver with the achieved simulation speed of 500μs in 10s computation time.

Analog Models Manipulation for Effective Integration in Smart System Virtual Platforms

“…SystemC, both plain [11] and with its AMS extension [10], has been used to model mixed-signal systems. However, none of the previous works provide automatic generation of Sys-temC AMS modules from previously designed analog models.…”

“…Similarly, for each contribution in the resulting set of relations, the algorithm tries to apply Rule 2 (Lines 7-10). Finally, if any modification of the input set occurred, the algorithm is recursively applied to the new set of relations (Lines [11][12]. This is necessary because both Rule 1 and Rule 2 may introduce new contributions, that must be normalized.…”