A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor

Abstract

Junctionless transistors, which do not have any pn junction in the source-channel-drain path have become an attractive candidate in sub-20 nm regime. They have homogeneous and uniform doping in source-channel-drain region. Despite some similarities with conventional MOSFETs, the charge-potential relationship is quite different in a junctionless transistor, due to its different operational principle. In this report, models for potential and drain current are formulated for shorter channel symmetric double-gate junctionless transistor (DGJLT). The potential model is derived from two dimensional Poisson's equation using "variable separation technique". The developed model captures the physics in all regions of device operation i.e., depletion to accumulation region without any fitting parameter. The model is valid for a range of channel doping concentrations, channel thickness and channel length. Threshold voltage and drain-induced barrier lowering values are extracted from the potential model. The model is in good agreement with professional TCAD simulation results.

Continuous and symmetric trans-capacitance compact model for triple-gate junctionless MOSFETs

“…Although there are numerous compact drain current models reported for JL transistors for long-channel [3][4][5][6][7][8][9][10] and short channel devices [11][12][13][14][15][16], the literature reveals only a handful of intrinsic capacitance models. For double-gate junctionless transistors, a charge based analytical model for long-channel devices has been developed in [17].…”

Semianalytical modeling of the depletion layers and their effects on the threshold voltage of a junctionless double‐gate MOSFET including trapped charges

“…Above the threshold, opposite charges accumulate near the surface and make moving charges appear in the Poisson's equation in addition to the doping charges. Some studies have developed the full rage current model for the JLDG MOSFETs where they have used the Pao‐Sah's dual integral current model, which is valid for all working conditions . In these models, the Gauss's law is applied to the surface and the surface and center electric fields and accumulated charges in the channel are calculated.…”

Triple-gate junctionless MOSFETs

“…Few models have been reported for short-channel JL DG MOSFETs, which are semi-analytical [75] or analytical limited in the subthreshold regime [76]. Recently, analytical drain current models based on the charge densities at the source and drain terminals have been developed for short-channel JL triple-gate (TG) transistors [12], [59],…”

“…From the compact models developed for long-channel [59], [69]- [72], [74], [76], [148] and short channel [60]- [62], [73], [75], [149] junctionless transistors (JLTs) either surface potential-based or charge-based, few of them try to assess the symmetry condition so far. The symmetry of the drain current compact models for long-channel [148] and short-channel [149] double-gate JLTs has been verified by passing the GST for drain current second and first order derivatives, respectively.…”

“…Although there are numerous compact drain current models reported for JL transistors for long-channel [59], [69][70][71][72], [74], [76], [148] and short channel devices [60][61][62], [73], [75], [149] the literature reveals only a handful of intrinsic capacitance models.…”