A Sub-Sampling-Assisted Phase-Frequency Detector for Low-Noise PLLs With Robust Operation Under Supply Interference

Hsu, Chun‐Wei; Tripurari, Karthik; Yu, Shih-An; Kinget, Peter R.

doi:10.1109/tcsi.2014.2359719

Cited by 55 publications

(23 citation statements)

References 11 publications

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“…9, showing a close-in fractional spur with power level of -49 dBc at 3.12 MHz. To demonstrate the effectiveness of our proposed soft loop switching scheme, a perturbation on VCO's power supply is injected periodically in a way similar to [3]. Interestingly, our programmable loop controller is able to mimic the case of prior-art SSPLL using a large dead-zone of Tref/2 in PFD as proposed in [2] by setting the switching threshold to VCC/2.…”

Section: Cap Interp Netorkmentioning

confidence: 99%

“…Moreover, potentially a long relocking time is required as phase errors may need to accumulate for quite some time before the dead-zone is passed and the FLL is switched on. This was solved in [3] by keeping both the FPL and SSL always on. In this paper, an automatic soft switching scheme is proposed to ensure agile and robust locking for improved SSPLL stability.…”

Section: Introductionmentioning

confidence: 99%

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Multi-phase sub-sampling fractional-N PLL with soft loop switching for fast robust locking

Liao

Dai

Nauta

et al. 2017

2017 IEEE Custom Integrated Circuits Conference (CICC)

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This paper presents a low phase noise sub-sampling PLL (SSPLL) with multi-phase outputs. Automatic soft switching between the sub-sampling phase loop and frequency loop is proposed to improve robustness against perturbations and interferences that may cause a traditional SSPLL to lose lock. A quadrature LC oscillator with capacitive phase interpolation network is employed to generate multi-phase outputs, which are further utilized to achieve fractional-N frequency synthesis. Implemented in a 130nm CMOS technology, the SSPLL chip is able to achieve a measured in-band phase noise of -120 dBc/Hz and a measured integrated jitter of 209 fs at 2.4 GHz, while consuming 27.2 mW with 16 output phases. The measured reference spur and fractional spur level is -72 dBc and -49 dBc, respectively.Index Terms -phase locked loop, subsampling, fractional-N, stability, multi-phase VCO, phase detector, jitter.

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Section: Cap Interp Netorkmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Multi-phase sub-sampling fractional-N PLL with soft loop switching for fast robust locking

Liao

Dai

Nauta

et al. 2017

2017 IEEE Custom Integrated Circuits Conference (CICC)

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“…It is instrumental to compare the β CP between the classical PFD/CP PLL and the SSPLL using (3) and 11:…”

Section: The Timing Error δT Between Vco and Ref Is Thus Translated Tmentioning

confidence: 99%

“…by intentionally adding a large dead zone (DZ) to the FLL PFD/CP (see [2] for the implementation), so that it will inject no current once the phase error is small and fall within the DZ. However, the work in [3] shows that Fig. 8 would also work with no DZ because around the locking point β CP,SS can be much larger than β CP,PFD anyway.…”

Section: The Timing Error δT Between Vco and Ref Is Thus Translated Tmentioning

confidence: 99%

“…The PD and CP noise is shown to be not multiplied by N 2 , and greatly attenuated by the high phase detection gain, leading to lower in-band phase noise and better PLL FOM. This article reviews the development of the sub-sampling PLL techniques and their applications in recent PLL architectures [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21]. Section II discusses the classical charge pump PLL.…”

Section: Introductionmentioning

confidence: 99%

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Sub-sampling PLL techniques

Gao

Klumperink

Nauta

2015

2015 IEEE Custom Integrated Circuits Conference (CICC)

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In a classical PLL, the phase detector (PD) and charge pump (CP) noise is multiplied by N 2 , when referred to the VCO output, due to the divide-by-N in the feedback path. It often dominates the in-band phase noise and limits the achievable PLL jitter•power Figure-Of-Merit (FOM). A subsampling PLL uses a PD that sub-samples the high frequency VCO output with the reference clock. The PD and CP noise in this PLL is shown to be not multiplied by N 2 , and greatly attenuated by the high phase detection gain, leading to lower in-band phase noise and better PLL FOM. This article reviews the development of the PLL FOM, the sub-sampling PLL techniques and their applications in recent PLL architectures.

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