A state-of-the-art hotspot recognition system for full chip verification with lithographic simulation

Abstract

In today's semiconductor industry, prior to wafer fabrication, it has become a desirable practice to scan layout designs for lithography-induced defects using advanced process window simulations in conjunction with corresponding manufacturing checks. This methodology has been proven to provide the highest level of accuracy when correlating systematic defects found on the wafer with those identified through simulation. To date, when directly applying this methodology at the full chip level, there has been unfavorable expenses incurred that are associated with simulation which are currently overshadowing its primary benefit of accuracy -namely, long runtimes and the requirement for an abundance of cpus. Considering the aforementioned, the industry has begun to lean towards a more practical application for hotspot identification that revolves around topological pattern recognition in an attempt to sidestep the simulation runtime. This solution can be much less costly when weighing against the negative runtime overhead of simulation. The apparent benefits of pattern matching are, however, counterbalanced with a fundamental concern regarding detection accuracy; topological pattern identification can only detect polygonal configurations, or some derivative of a configuration, which have been previously identified. It is evident that both systems have their strengths and their weaknesses, and that one system's strength is the other's weakness, and vice-versa.A novel hotspot detection methodology that utilizes pattern matching combined with lithographic simulation will be introduced. This system will attempt to minimize the negative aspects of both pattern matching and simulation. The proposed methodology has a high potential to decrease the amount of processing time spent during simulation, to relax the high cpu count requirement, and to maximize pattern matching accuracy by incorporating a multi-staged pattern matching flow prior to performing simulation on a reduced data set. Also brought forth will be an original methodology for constructing the core pattern set, or candidate hotspot library, in conjunction with establishing hotspot and coldspot pattern libraries. Lastly, it will be conveyed how this system can automatically improve its potential as more designs are passed through it.

Integration of pattern matching into verification flows

“…In [2], pattern matching is used to detect hot spots in full lithographic verification flows, an idea which is aligned with one of the applications we are proposing in the scope of this work. The same idea was proposed in [3], but it was more towards LFD flows which are a fast version of verification ones.…”

Design space exploration for early identification of yield limiting patterns

“…However, for advanced nodes (14nm and beyond) the number of pattern continues to rapidly increase. Comprehensive and compact test patterns are crucial to the development of new semiconductor technology [1] [2]. For this reason, the need for exploring the design space to find patterns that are candidate for hotspots is very important.…”

<title>Clean pattern matching for full chip verification</title>

“…Six times increase is not acceptable for market requirement and product development period and so far several methods have been discussed to reduce LCC time. "Pattern matching" is one of the candidates and its conventional flow consists 1 Satomi Nakamura: satomi1.nakamura@toshiba.co.jp 2 Chikaaki Kodama: chikaaki1.kodama@toshiba.co.jp of the following three steps; [3][4][5] (1) define hotspots on preceding LCC and/or experimental data (2) store the hotspots into a library (3) verify whether the same patterns exist or not in layouts in a pattern matching method with a hotspot library (Hotspot matching). This method needs to run LCC to find new and unknown hotspots in the unmatched area as shown in Fig.2.…”