1980
DOI: 10.1109/isscc.1980.1156087
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Abstract: THIS PAPER will discuss a dynamic memory structure capable of constructing 1Mb VLSI 10 x lOmm memory chips in conventional photolithography, whose operational margin is within 2pm design. Figure 1 shows the structure of 2 bits of a one-transistor one-capacitor memory cell. The cell consists of a Quadruply Self Aligned (QSA) RIOSFET', a stacked high storage ~a p a c i t o r~'~ of tantalum oxide, a poly Si word line and an A1 bit line. aligned contact of QSA MOS' and high capacitance stacked capacitor structure…

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