A Single DC Source Cascaded Seven-Level Inverter Integrating Switched-Capacitor Techniques

Sun, Xiaofeng; Wang, Baocheng; Zhou, Yue; Wang, Wei; Du, Huiyuan; Lu, Zhengding

doi:10.1109/tie.2016.2557317

Cited by 182 publications

(107 citation statements)

References 24 publications

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“…Table presents the comparative results. From the table, it is observed that all structures excluding structures proposed in previous studies possess fault‐tolerant feature. Further, it can be concluded that except the topology in Choi and Kang, the proposed FT structures have employed minimum number of devices (switches and driver units).…”

Section: Comparative Assessmentmentioning

confidence: 99%

Modified reduced device multilevel inverter structures with open circuit fault‐tolerance capabilities

Dewangan

Gupta

Bhatnagar³

2019

Int Trans Electr Energ Syst

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Summary Reliability and large number of components are major challenges for multilevel inverters being used in many industrial applications. These inverters may face situations like failure of power switches, which, in turn, can cause severe damage to other equipment of the system. Hence, it is important these inverters are fault‐tolerant. In this article, some of the recently proposed reduced device multilevel inverter (RD‐MI) topologies are considered and analyzed in light of imparting open circuit fault‐tolerance capability. In RD‐MIs, the occurrence of faults would cause a shutdown of the system due to the lack of redundant switching states. However, for the cases involving “any single open‐switch failure (SOSF),” the system can continue to operate uninterrupted by imparting fault‐tolerant (FT) feature to the RD‐MIs. With the proposed solution, the complete system shutdown can be avoided, thereby achieving higher reliability. In this work, two RD‐MIs are chosen to demonstrate the proposed approach. Further, the proposed FT RD‐MIs based on suggested FT strategy under the healthy and abnormal modes are simulated using MATLAB/Simulink software. The obtained simulation results are experimentally validated.

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Section: Comparative Assessmentmentioning

confidence: 99%

Modified reduced device multilevel inverter structures with open circuit fault‐tolerance capabilities

Dewangan

Gupta

Bhatnagar³

2019

Int Trans Electr Energ Syst

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“…More is the number of switches, DC sources, and diodes, more will be the cost of an MLI. Figure 10a shows the proposed RS MLI uses least number of switches compared to the wellknown MLIs 'T1' in Chattopadhyay and Chakraborty [22], 'T2' in Lee et al [23], 'T3' in Samadaei et al [24], 'T4' in Sun et al [25], 'T5' in Babaei et al [26], and 'T6' in Ye et al [27]. The proposed RS MLI and T6 have identical switch count for all N l , and due to which these can be a preferred alternative to the conventional MLIs in medium/high voltage applications.…”

Section: Reduced Switch Multilevel Inverter (Rs Mli)mentioning

confidence: 99%

Reduced switches multilevel inverter integration with boost converters in photovoltaic system

2019

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Multilevel inverters (MLIs) are developed to meet medium voltage and high power applications in flexible power systems. The conventional configuration of multilevel inverter requires more switches and has limitation to its wide range application. This paper reports the performed work on 1-phase 7-level reduced switch multilevel inverter (RS MLI) in photovoltaic (PV) system. RS MLI configuration integration with PV system which uses less number of switching components for specified number of voltage output levels as compared to that of conventional multilevel inverter topology. To performed enhanced operation of PV cells and maximize the solar energy extraction an incremental conductance based maximum power point tracking scheme is used. To improve the quality of RS MLI output parameters mainly total harmonic distortion and switching losses, selected harmonic elimination based genetic algorithm method is consider for control the gating pulse of PV based RS MLI. This work is performed using MATLAB/SIMULINK software. Keywords Reduced switch multilevel inverter (RS MLI) • Maximum power point tracking (MPPT) • Incremental conductance (IC) • Genetic algorithm (GA) • Total harmonic distortion (THD)

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“…A new cascaded seven-level inverter is developed in [21]. It uses single dc source and switched capacitor technique.…”

Section: Related Workmentioning

confidence: 99%

Novel Basic Block of Multilevel Inverter Using Reduced Number of On-State Switches and Cascaded Circuit Topology

Prayag

Bodkhe²

2017

Advances in Electrical Engineering

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In this paper a basic block of novel topology of multilevel inverter is proposed. The proposed approach significantly requires reduced number of dc voltage sources and power switches to attain maximum number of output voltage levels. By connecting basic blocks in series a cascaded multilevel topology is developed. Each block itself is also a multilevel inverter. Analysis of proposed topology is carried out in symmetric as well as asymmetric operating modes. The topology is investigated through computer simulation using MATLAB/Simulink and validated experimentally on prototype in the laboratory.

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A Single DC Source Cascaded Seven-Level Inverter Integrating Switched-Capacitor Techniques

Cited by 182 publications

References 24 publications

Modified reduced device multilevel inverter structures with open circuit fault‐tolerance capabilities

Modified reduced device multilevel inverter structures with open circuit fault‐tolerance capabilities

Reduced switches multilevel inverter integration with boost converters in photovoltaic system

Novel Basic Block of Multilevel Inverter Using Reduced Number of On-State Switches and Cascaded Circuit Topology

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