A single-chip hybrid media processor for CRT and matrix displays-based televisions

Rathnam, S.; Slavenburg, G.; Nayak, Suraj Kumar; Bellers, Erwin B.; Janssen, J.H.

doi:10.1109/icce.2003.1219001

Cited by 2 publications

(3 citation statements)

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“…Should that not be the case, the above ratio is even bigger than which even more emphasizes the need for the second level of memory hierarchy. Similarly is defined the ratio between the computed number of accesses for the meandering scanning style and the minimal number of accesses: (8) This analysis highlights the need for a second level of the memory subsystem. The L1 scratchpad provides a block-column or a block-row refill of L0 scratchpad.…”

Section: A Internal Bandwidthmentioning

confidence: 99%

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Memory-centric video processing

Beric¹,

Meerbergen

Haan

et al. 2008

IEEE Trans. Circuits Syst. Video Technol.

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This work presents a domain-specific memory subsystem based on a two-level memory hierarchy. It targets the application domain of video post-processing applications including video enhancement and format conversion. These applications are based on motion compensation and/or broad class of content adaptive filtering to provide the highest quality of pictures. Our approach meets the required performance and has sufficient flexibility for the application domain. It especially aims at the implementation-wise most challenging applications: compute-intensive and bandwidth-demanding applications that provide the highest quality at high picture resolutions. The lowest level of the memory hierarchy, closest to the processing element, the L0 scratchpad, is organized specifically to enable fast retrieval of an arbitrarily positioned 2-D block of pixels to the processing element. To guarantee the performance, most of its addressing logic is hardwired, leaving a user a set of API for initialization and storing/loading the data to/from the L0 scratchpad. The next level of the memory hierarchy, the L1 scratchpad, minimizes the off-chip memory bandwidth requirements. The L1 scratchpad is organized specifically to enable efficient aligned block-based accesses. With lower data rates compared to the L0 scratchpad and aligned block access, software-based addressing is used to enable full flexibility. The two-level memory hierarchy exploits prefetching to further improve the performance.Index Terms-Computer architecture, memory architecture, motion estimation, memory hierarchy, memory subsystem, scratchpad memory, video signal processing.

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Section: A Internal Bandwidthmentioning

confidence: 99%

“…The L0 scratchpad is scanning the picture portion within the L1 scratchpad block-by-block, e.g., left-to-right-top-to-bottom (LRTB), or meandering. By doing so, the high memory bandwidth needed for a L0 refill [see (8)] is not exposed to the off-chip memory.…”

Section: A Region-based Approachmentioning

confidence: 99%

Memory-centric video processing

Beric¹,

Meerbergen

Haan

et al. 2008

IEEE Trans. Circuits Syst. Video Technol.

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“…The displays commonly used are liquid crystal display ͑LCD͒, plasma display panel ͑PDP͒, vacuum fluorescent display ͑VFD͒, cathode ray tube ͑CRT͒, field emission display ͑FED͒, and electroluminescent display ͑ELD͒. [1][2][3][4] Except for the LCD, these displays use self-emission. In the structure of self-emitted displays, there is a phosphor layer constructed which is an important part for the display system.…”

mentioning

confidence: 99%

Novel SrGa[sub 2]O[sub 4] Phosphor for Tunable Blue-White Luminescence

Yang

2005

J. Electrochem. Soc.

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A tunable blue to blue-white SrGa 2 O 4 phosphor was prepared with a solid-state reaction method by varying the composition concentration of source materials. The decomposition temperature and weight loss of Ga 2 O 3 and SrCO 3 were evaluated by thermogravimetric analysis. The deficiency of Ga in SrGa 2 O 4 phosphor can be compensated by increasing the molar ratio of Ga 2 O 3 /SrCO 3 . Photoluminescence measurements show that Ga is the luminescence center of strontium gallate phosphor. When the molar ratio of Ga 2 O 3 /SrCO 3 is 1, the emission wavelength of SrGa 2 O 4 phosphor is ϳ402 nm, which is referred to the 4 T 1 → 4 A 2 transition of electrons in Ga d orbits. Crystallization of SrGa 4 O 7 was observed as the phosphor was prepared at a higher molar ratio of Ga 2 O 3 /SrCO 3 . The ligand field and the electron transferring mechanism in Ga will be modulated by the development of SrGa 4 O 7 . Thus, the emission wavelength of phosphor is altered from 402 to 430 nm where the electron is transferred from 4 T 2A exciting state to 4 A 2 ground state while the emission spectrum is broadened.

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A single-chip hybrid media processor for CRT and matrix displays-based televisions

Cited by 2 publications

References 0 publications

Memory-centric video processing

Memory-centric video processing

Novel SrGa[sub 2]O[sub 4] Phosphor for Tunable Blue-White Luminescence

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