A Single-Chip 125-MHz to 32-GHz Signal Source in 0.18-$\mu$m SiGe BiCMOS

Yu, Shih-An; Baeyens, Y.; Weiner, J. S.; Koc, Ut-Va; Rambaud, M.; Liao, Fang-Ren; Chen, Young-Kai; Kinget, Peter R.

doi:10.1109/jssc.2011.2104551

Cited by 34 publications

(7 citation statements)

References 20 publications

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“…Generally, the FS in software-defined radio (SDR) is composed of a narrow band phase locked loop (PLL) and post synthesis circuit [ 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 ]. Compared with a wideband PLL employing multiple voltage controlled oscillator (VCO) cores, the PLL in this FS structure characterizes relatively constant loop parameters and releases the requirement for the oscillator.…”

Section: Introductionmentioning

confidence: 99%

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A Quadrature Single Side-Band Mixer with Passive Negative Resistance in Software-Defined Frequency Synthesizer

Zhang

2018

Sensors

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Software-defined radio (SDR) is a good solution for complying with the existing and incoming protocols for emerging wireless sensor networks (WSN) and internet of things (IoT) applications. The frequency synthesizer in a SDR tranceiver usually consists of a phase locked loop (PLL) and a post synthesizer. The PLL is the narrow band signal source and the post synthesizer generates wideband outputs by mixing and dividing. Compared with a frequency synthesizer utilizing the wideband PLL, this synthesizer features relatively constant loop parameters and mitigates the requirement for the oscillator. In this paper, a quadrature single side-band (QSSB) mixer with the proposed passive negative resistance (PNR) for frequency mixing in a post synthesizer is presented. The PNR is achieved by biasing the Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET) of the cross-coupled pair at the deep-triode region periodically and incorporates an inductor and a cap-array as the mixer load. Compared with the traditional single side-band mixers utilizing Inductor-Capacitor (LC) resonant loads or quality factor enhanced (Q-enhanced) LC resonant loads, which suffer from a selectivity versus working range trade-off, the mixer employing the proposed loading structure provides not only a wide operating range, but also a superior image side-band rejection ratio (ISRR). Moreover, the oscillating risk in conventional mixers adopting Q-enhanced LC resonant loads is eliminated. A wideband frequency synthesizer employing the proposed mixer was implemented in a TSMC 0.18 µm CMOS process and the mixer performed ISRR of 40–57 dB and 30–57 dB across 2.5–3 GHz and 2.3–3.2 GHz, respectively. The power consumption of the QSSB mixer, including buffer, is 18 mA from a 1.8 V supply and the active area is 0.445 mm2. The measurement results provide validation that the proposed QSSB mixer is suitable for wideband software-defined frequency synthesizers and other frequency generating systems.

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Section: Introductionmentioning

confidence: 99%

“…Moreover, to obtain purity of LO signals, the image side-band signals should also be attenuated. The LC resonant loads are widely utilized in the QSSB mixer to pick out the desired signals [ 3 , 6 , 13 , 14 ]. However, the working range and the selectivity conflict with each other.…”

Section: Introductionmentioning

confidence: 99%

A Quadrature Single Side-Band Mixer with Passive Negative Resistance in Software-Defined Frequency Synthesizer

Zhang

2018

Sensors

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“…For ultra-wide bandwidth communication and RF automated test equipment, the high precision of α is indispensable, so that the input value of the DSM will be represented with many bits [9], [10]. The large-size accumulators and registers are included in the DSM.…”

Section: Introductionmentioning

confidence: 99%

Hardware Reduction of MASH Delta-Sigma Modulator Based on Partially Folded Architecture

Song

2015

IEEE Trans. Circuits Syst. II

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This brief presents a new multi-stage noise-shaping (MASH) structure which has less hardware by applying partially folded architecture. A folded MASH architecture that exploits adders in half is introduced, and the proposed architecture combines the folded MASH architecture and the conventional MASH architecture. The noise power spectrum of the proposed architecture is mathematically analyzed, and the noise-shaping capability of the MASH architecture is preserved. Index Terms-Delta-Sigma Modulator (DSM), Fractional-N Frequency Synthesizer, Multistage Noise Shaping (MASH) II. PREVIOUS DELTA-SIGMA MODULATORSThe first-order error feedback modulator (EFM) is a typical structure of the first-order DSM, which includes a quantizer, a register, and an adder with a feedback loop, as shown in Fig. 1(a). The first-order EFM is referred to as the EFM throughout this paper. In most applications, the input of the DSM is a fractional value in the range of [0, 1), represented in m bits, and the input x[n] is shifted left by m bits, ranging from 0 to (M-1), where M = 2 m . The input x[n] is accumulated and quantized by Q(·) that compares with a threshold value M. The output y[n] will be 1 if the accumulated value v[n] is equal to or greater than M. Otherwise, y[n] will be 0.After quantizing v[n], the remainder e[n] is sampled by a gray-colored register to feed it back to the input at the next cycle.

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“…The power consumption of the QVCO is also significantly increased compared to a single differential VCO. In the second topology, multi-band carrier generation is achieved using a set of differential VCOs, followed by VCO frequency division [13], [15]- [17]. This approach benefits from the absence of SSB mixing, thus avoiding undesired sidebands.…”

mentioning

confidence: 99%

“…2 shows a conceptual diagram of the proposed SDR frequency synthesizer. Unlike the present SDR frequency synthesizers, which contain two, or sometimes four, LC resonators [15], only one LC VCO is used in the core-PLL, which considerably reduces the occupied chip area. Moreover, a quadrature fractional-ILFD is proposed for quadrature output generation that avoids the use of poly-phase filters, which are narrow band with poor phase accuracy, and QVCOs, which degrade the phase noise characteristics.…”

mentioning

confidence: 99%

A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios

Deng

Hara

Musa

et al. 2014

IEEE J. Solid-State Circuits

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This paper describes a compact and low-power frequency synthesizer with quadrature phase output for software-defined radios (SDRs). The proposed synthesizer is constructed using a core phase-locked loop (PLL), which is coupled with a fractional-N injection-locked frequency divider (ILFD). The fractional-N injection-locking operation is achieved by the proposed self-synchronized gating injection technique. The principle of a fractional-N injection locking operation and the concept of the proposed circuits are described in detail. Analysis for predicting the locking range of the proposed fractional-N ILFD is investigated. A digital calibration scheme is adopted in order to compensate for process, voltage, and temperature (PVT) variations. Implemented in a 65 nm CMOS process, this work demonstrates continuous frequency coverage from 10 MHz to 6.6 GHz with quadrature phase output while occupying a small area of 0.38 mm 2 and consuming 16 to 26 mW, depending on the output frequency. The normalized phase noise achieves -135.3 dBc/Hz at an offset of 3 MHz and -95.1 dBc/Hz at an offset of 10 kHz, both from a carrier frequency of 1.7 GHz.

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A Single-Chip 125-MHz to 32-GHz Signal Source in 0.18-$\mu$m SiGe BiCMOS

Cited by 34 publications

References 20 publications

A Quadrature Single Side-Band Mixer with Passive Negative Resistance in Software-Defined Frequency Synthesizer

A Quadrature Single Side-Band Mixer with Passive Negative Resistance in Software-Defined Frequency Synthesizer

Hardware Reduction of MASH Delta-Sigma Modulator Based on Partially Folded Architecture

A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios

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