A Self-Healing, High Performance and Low-Cost Radiation Hardened Latch Design

Low cost and high performance double‐node upset resilient latch for low orbit space applications

“…However, the cell becomes completely upset after a weak SET at the sensitive node, and the robustness of the latch is similar to an unhardened latch. Single node upset self‐healing latch (SNUSH) 8 uses the ISInvs and CG‐CEs to form an interlocked feedback loop. The cell is completely resilient to SNU, but if the DNU affects the sensitive node pair, the latch fails to tolerate it.…”

“…Other hardware redundancy methods like modular redundancy, such as triple‐modular redundancy (TMR), and 5‐MR can also mask the SEs; however, the approach is not affordable for resource‐constraint applications 6 . Radiation hardening by design (RHBD) is a low‐cost approach to circuit‐level hardening that has been widely studied in recent technical literature 7–15 …”

“…Using the RHBD approaches, single node upset (SNU) hardened latches such as SEUT, 7 SNUSH, 8 and RH‐1 9 have recently been proposed. However, aggressive scaling of technology node has also raised the concern of multinode upsets (MNU) 1–4,10,11 .…”

“…6 Radiation hardening by design (RHBD) is a low-cost approach to circuit-level hardening that has been widely studied in recent technical literature. [7][8][9][10][11][12][13][14][15] Using the RHBD approaches, single node upset (SNU) hardened latches such as SEUT, 7 SNUSH, 8 and RH-1 9 have recently been proposed. However, aggressive scaling of technology node has also raised the concern of multinode upsets (MNU).…”

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness

“…Therefore, in order to provide highly reliable integrated circuits, it is necessary to design storage cells that can tolerate and even recover from MNU. To provide radiation hardening capability, researchers have proposed a series of radiation-hardened circuit structures [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. Some of them use time redundancy, e.g., using delay elements as error-filterable components [8], some use pulse detection technology, such as that in [9], and some use space redundancy, e.g., introducing redundant storage nodes and/or triple-moduleredundancy (TMR) along with voting circuits [10][11][12][13][14].…”