International Electron Devices Meeting. IEDM Technical Digest
DOI: 10.1109/iedm.1997.650501
|View full text |Cite
|
Sign up to set email alerts
|

A selective-epitaxial SiGe HBT with SMI electrodes featuring 9.3-ps ECL-gate delay

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

0
8
0

Publication Types

Select...
5
1
1

Relationship

1
6

Authors

Journals

citations
Cited by 30 publications
(8 citation statements)
references
References 5 publications
0
8
0
Order By: Relevance
“…The 0.6-m-wide SiGe-base and Si-cap multilayer, self-aligned to the 0.2-m-wide emitter, was selectively epitaxially grown by using a UHV/CVD system. The collector capacitance and base resistance were effectively reduced by using a poly-Si assisted selfaligned SEG (PASS) structure [2]. To reduce the parasitic resistances of all the electrodes, Ti-salicide layers were formed.…”
Section: Self-aligned Seg Sige Hbtmentioning
confidence: 99%
“…The 0.6-m-wide SiGe-base and Si-cap multilayer, self-aligned to the 0.2-m-wide emitter, was selectively epitaxially grown by using a UHV/CVD system. The collector capacitance and base resistance were effectively reduced by using a poly-Si assisted selfaligned SEG (PASS) structure [2]. To reduce the parasitic resistances of all the electrodes, Ti-salicide layers were formed.…”
Section: Self-aligned Seg Sige Hbtmentioning
confidence: 99%
“…In particular, the SiGe base HBT can improve its speed dramatically over the Si bipolar transistor (BJT). Further, the gate delay for ECL circuits is less than 10 ps, comparable to that of compound semiconductors [6,7], and cutoff frequencies exceeding 100 GHz [8] have been reported. Further, by the use of the heterojunction, the freedom in the design of the transistor has been increased so that many requirements can be dealt with.…”
Section: Introductionmentioning
confidence: 99%
“…This approach has the advantage of being compatible with conventional double polysilicon bipolar technology, which minimizes parasitic collector/base capacitance and gives very fast digital circuit performance. ECL gate delays of 11 ps [5] and 9.3 ps [6] have been reported for this approach.…”
mentioning
confidence: 99%
“…delays around 10 ps [5], [6] and high frequency analog circuits for wireless communication systems [7]. However, in spite of this impressive progress, no single process architecture has yet emerged as the dominant approach for manufacturing SiGe HBT integrated circuits.…”
mentioning
confidence: 99%
See 1 more Smart Citation