A CPU‐FPGA heterogeneous approach for biological sequence comparison using high‐level synthesis

Abstract

Summary This article presents a high‐level synthesis implementation of the longest common subsequence (LCS) algorithm combined with a weighted‐based scheduler for comparing biological sequences prioritizing energy consumption or execution time. The LCS algorithm has been thoroughly tailored using Vivado High‐Level Synthesis tool, which is able to synthesize register transfer level (RTL) from high‐level language descriptions, such as C/C++. Performance and energy consumption results were obtained with a CPU Intel Core i7‐3770 CPU and an Alpha‐Data ADM‐PCIE‐KU3 board that has a Xilinx Kintex UltraScale XCKU060 FPGA chip. We executed a batch of 20 comparisons of sequences on 10k, 20k, and 50k sizes. Our experiments showed that the energy consumption on the combined approach was significantly lower when compared to the CPU, achieving 75% energy reduction on 50k comparisons. We also used the tool proposed in this article to do a case study on Covid‐19, with real SARS‐CoV‐2 sequences, comparing their LCS scores.

An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment

“…Some of the earlier works on sequence alignment tried to fully optimize the FPGA LUTs by doing custom optimizations using simple cost models, like the edit-distance, the Levenshtein distance [39] or being limited to compute the longest common subsequence [40]. Despite their good performance, these solutions do not fulfill the requirements of modern bioinformatics tools due to algorithmic limitations.…”

Special Issue on High‐end Heterogeneous Architectures, Methodologies, and Algorithms (HHAMA20)

“…The achieved benefit depends on the relationship between the computing power of CPUs and GPUs. Moreover, this gain entails the growth of the average power that increases the energy consumed during the application execution. In Reference 10, the authors present a high‐level synthesis (HLS) implementation of the longest common subsequence (LCS) algorithm combined with a weighted‐based scheduler for the comparison of biological sequences prioritizing energy consumption or execution time. The LCS algorithm has been thoroughly tailored using the Vivado high‐level synthesis tool, which can synthesize the register transfer level (RTL) from high‐level language descriptions, such as C/C++.…”