A Route to Chaos Using FPGAs

Abstract

About this SeriesThe Emergence, Complexity and Computation (ECC) series publishes new developments, advancements and selected topics in the fields of complexity, computation and emergence. The series focuses on all aspects of reality-based computation approaches from an interdisciplinary point of view especially from applied sciences, biology, physics, or chemistry. It presents new ideas and interdisciplinary insight on the mutual intersection of subareas of computation, complexity and emergence and its impact and limits to any computing based on physical limits (thermodynamic and quantum limits, Bremermann's limit, Seth Lloyd limits…) as well as algorithmic limits (Gödel's proof and its impact on calculation, algorithmic complexity, the Chaitin's Omega number and Kolmogorov complexity, non-traditional calculations like Turing machine process and its consequences,…) and limitations arising in artificial intelligence field. The topics are (but not limited to) membrane computing, DNA computing, immune computing, quantum computing, swarm computing, analogic computing, chaos computing and computing on the edge of chaos, computational aspects of dynamics of complex systems (systems with self-organization, multiagent systems, cellular automata, artificial life,…), emergence of complex systems and its computational aspects, and agent based computation. The main aim of this series it to discuss the above mentioned topics from an interdisciplinary point of view and present new ideas coming from mutual intersection of classical as well as modern methods of computation. Within the scope of the series are monographs, lecture notes, selected contributions from specialized conferences and workshops, special contribution from international experts.More information about this series at

Realizing Chaotic Systems on Field Programmable Gate Arrays: An Introduction

“…A further detailed discussion of FPGA architecture, 3 effects of sampling clock and data path quantization is beyond the scope of this chapter, for details, please refer to [2]. We can however continue to the next step: simulating the discretized Ikeda DDE.…”

“…The hardware platform that we will use in this chapter is a DE2-115 board from Terasic corporation that incorporates a Cyclone IV FPGA from Altera [2]. This platform highlights the hardware requirements for implementing nonlinear ODEs: a modern FPGA that has on-chip peripherals such as Phase-Locked Loops (PLLs), multipliers and RAM blocks.…”

“…To complete the implementation of a nonlinear (chaotic) differential equation on an FPGA, the following steps are required: The next few section(s) will illustrate the steps above, using the Ikeda DDE [2] as an example:…”

“…Although the entire design can be implemented within the FPGA software framework provided by the FPGA vendor, utilizing Simulink will illustrate the power of abstraction, that has become so prevalent in twenty-first century FPGA designs. Hardware block diagram for specifying nonlinear ODEs using forward-Euler's method [2]. We have highlighted the vector nature of xN New and xN from Eqs.…”

“…Simulating a DDE in Simulink, block diagram adopted from [2]. We utilize the discrete-time integrator but inherit the sample time from the fixed-point simulation period The large file size is because the reference design is fully synthesized for Quartus version 12.0. and the design also implements other DDEs (refer to Sect.…”