A retargetable parallel-programming framework for MPSoC

Abstract

As more processing elements are integrated in a single chip, embedded software design becomes more challenging: It becomes a parallel programming for nontrivial heterogeneous multiprocessors with diverse communication architectures, and design constraints such as hardware cost, power, and timeliness. In the current practice of parallel programming with MPI or OpenMP, the programmer should manually optimize the parallel code for each target architecture and for the design constraints. Thus, the design-space exploration of MPSoC (multiprocessor systems-on-chip) costs become prohibitively large as software development overhead increases drastically. To solve this problem, we develop a parallel-programming framework based on a novel programming model called common intermediate code (CIC). In a CIC, functional parallelism and data parallelism of application tasks are specified independently of the target architecture and design constraints. Then, the CIC translator translates the CIC into the final parallel code, considering the target architecture and design constraints to make the CIC retargetable. Experiments with preliminary examples, including the H.263 decoder, show that the proposed parallel-programming framework increases the design productivity of MPSoC software significantly.

Systematic integration of flowgraph- and module-level parallelism in implementation of DSP applications on multiprocessor systems-on-chip

“…The resulting parallel C code is then compiled for the target platform. Kwon [6] introduces the Common Intermediate Code (CIC) layer to interface software and hardware. Software is first partitioned and then written in CIC using generic application programming interfaces (APIs) for intertask communication and synchronization.…”

OpenMDSP: Extending OpenMP to Program Multi-Core DSP

“…Regarding the portability of programming model, researchers also proposed a retargetable parallel programming framework for MPSoC [24]. They designed common intermediate code (CIC) and developed a framework to map task codes to CIC.…”

Middleware approaches for adaptivity of Kahn Process Networks on Networks-on-Chip

“…Previous research on the use of KPNs in multiprocessor embedded devices has been mainly focusing on the design of frameworks which employ them as a model for application specification [4], [5], [6], and which aim at supporting and optimizing the mapping of KPN processes on the nodes of a reference platform [7], [8]. In [4], [5], different methods and tools are proposed for automatically generating KPN application models from programs written in C/C++.…”

“…Design space exploration tools and performance analysis are then usually employed for optimizing the mapping of the generated KPN processes on a reference platform. A design phase usually follows in which software synthesis for multiprocessor systems [6], [8], or architecture synthesis for FPGA platforms [4] is implemented.…”