A practical evaluation of the performance of the Impulse CoDeveloper HLS tool for implementing large-kernel 2-D filters

Colodro-Conde, Carlos; Toledo-Moreo, F. Javier; Toledo-Moreo, R.; Martínez-Álvarez, J. Javier; Garrigós-Guerrero, J.; Vicente, José Manuel Ferrández

doi:10.1007/s11554-013-0374-x

Cited by 3 publications

(2 citation statements)

References 23 publications

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“…The authors performed the convolution operation for a 384×286 pixel resolution images with a 1.69 ms runtime and a 5×5 convolution kernel. Finally, in [6] it is described the design of 2D convolution filters with large kernels, up to 50×50 coefficients, using the Impulse CoDeveloper TM high-level synthesis (HLS) tool. The authors provide a practical guide for designers willing to make the most of an HLS tool like Impulse CoDeveloper, and compare the results, in terms of area utilization, minimum clock period and power consumption, with implementations developed using lower-level design tools.…”

Section: Related Workmentioning

confidence: 99%

An FPGA 2D-convolution unit based on the CAPH language

Aguilar-González

Arias-Estrada

Pérez-Patricio

et al. 2015

J Real-Time Image Proc

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International audienceConvolution is an important operation in image processing applications, such as edge detection, sharpening , adding blurring and so on. Convolving video streams in real-time is a challenging task for PC systems, however, FPGA devices can successfully be used in these tasks. In this article, the design and implementation of a reconfigurable FPGA architecture for 2D-convolution filtering is described. The filtered frames are calculated at a rate of 103 frames per second for images up to 1200×720 pixel resolution. By using a shift-based arithmetic and circular buffers, the developed FPGA architecture allows to reduce the hardware resources consumption up to 98% compared to the conventional convolution implementations , provides high speed processing and enables to manage large number of different convolution kernels. On the other hand, by using the CAPH language it is possible to reduce the design time up to 75% compared to the plain VHDL design. Furthermore, to maintain high flexibility in concordance with the input video, the developed hardware allows to configure the resolution of the input images with values of 3 × Y up to 1200 × Y , and allows scalability for different sizes of convolution kernels of simple and systematic form. Finally , the developed FPGA architecture for the proposed method was implemented and validated in an FPGA Cyclone II EP2C35F672C6 embedded in an Altera development board DE2

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Section: Related Workmentioning

confidence: 99%

An FPGA 2D-convolution unit based on the CAPH language

Aguilar-González

Arias-Estrada

Pérez-Patricio

et al. 2015

J Real-Time Image Proc

View full text Add to dashboard Cite

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“…The key point of this approach is to incorporate the high-level synthesis process into the design flow to automatically generate register-level languages from C-like languages, which have a higher abstraction level related to the former [ 24 ]. It is highly promising for complex FPGA designs [ 25 , 26 , 27 , 28 ]. It can effectively raise the development productivity by enabling the users to focus only on the algorithm level instead of the hardware level constraints, such as data flow, logic control or interface protocol.…”

Section: Introductionmentioning

confidence: 99%

Embedded Implementation of VHR Satellite Image Segmentation

Balla-Arabé

Ginhac

et al. 2016

Sensors

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Processing and analysis of Very High Resolution (VHR) satellite images provide a mass of crucial information, which can be used for urban planning, security issues or environmental monitoring. However, they are computationally expensive and, thus, time consuming, while some of the applications, such as natural disaster monitoring and prevention, require high efficiency performance. Fortunately, parallel computing techniques and embedded systems have made great progress in recent years, and a series of massively parallel image processing devices, such as digital signal processors or Field Programmable Gate Arrays (FPGAs), have been made available to engineers at a very convenient price and demonstrate significant advantages in terms of running-cost, embeddability, power consumption flexibility, etc. In this work, we designed a texture region segmentation method for very high resolution satellite images by using the level set algorithm and the multi-kernel theory in a high-abstraction C environment and realize its register-transfer level implementation with the help of a new proposed high-level synthesis-based design flow. The evaluation experiments demonstrate that the proposed design can produce high quality image segmentation with a significant running-cost advantage.

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Fast FPGA prototyping for real-time image processing with very high-level synthesis

Marzani

et al. 2017

J Real-Time Image Proc

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A practical evaluation of the performance of the Impulse CoDeveloper HLS tool for implementing large-kernel 2-D filters

Cited by 3 publications

References 23 publications

An FPGA 2D-convolution unit based on the CAPH language

An FPGA 2D-convolution unit based on the CAPH language

Embedded Implementation of VHR Satellite Image Segmentation

Fast FPGA prototyping for real-time image processing with very high-level synthesis

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