Networks-on-Chip (NoC) has been proposed as a solution for addressing the design challenges of future highperformance nanoscale architectures. Innovative systemlevel performance models are required for designing NoC based architectures. This paper presents a VHDL based cycle accurate register transfer level model for evaluating the latency, throughput, dynamic, and leakage power consumption of NoC based interconnection architectures. We implemented a parameterized register transfer level design of the NoC arc…
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