A parallel architecture of interpolated timing recovery for high- speed data transfer rate and wide capture-range

Study of Interpolated Timing Recovery Phase-Locked Loop with Linearly Constrained Adaptive Prefilter for Higher-Density Optical Disc

“…In general, MMSE ITR PLL with a linearly constrained adaptive Volterra filter read channel includes four main technical components: (i) ITR PLL, [4][5][6] (ii) MMSE adaptive filter placed before ITR PLL, 5) (iii) AVF, 12) and (iv) LCAF. 10,11) In this paper, we concentrate on the theory of (iv) because the references of (i)-(iii) are very well described articles and we can refer to these references easily.…”

“…The FDTS also has a shorter decision delay than VD for minimizing loop delay. The phase error is calculated by the decision-directed timing error detection method 6,13,14) for the PR-equalized signal. The fractional sample second-order AVF 12) is placed before the interpolator of ITR PLL.…”

“…An interpolated timing recovery (ITR) algorithm [4][5][6] has been investigated as an effective digital PLL system for data storage because of its simple mathematical expression. The ITR PLL system has been actively studied for magnetic 5) and optical 6) data storage systems.…”

“…An interpolated timing recovery (ITR) algorithm [4][5][6] has been investigated as an effective digital PLL system for data storage because of its simple mathematical expression. The ITR PLL system has been actively studied for magnetic 5) and optical 6) data storage systems. On the other hand, one of the key factors of improved PLL schemes is the combination of the adaptive equalization of the read back signal before the calculation of the phase error.…”