A novel technique for noise-tolerance in dynamic circuits

Goel, S.; Darwish, T.; Bayoumi, Magdy

doi:10.1109/isvlsi.2003.1183465

Cited by 4 publications

(2 citation statements)

References 7 publications

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“…The first category of circuits were developed to reduce the propagated noise of dynamic gates by (a) dynamically increasing the switching threshold and (b) precharging intermediate nodes to increase the body effect [15,1,5,3,4]. These methods do nothing to improve coupling noise, and have a relatively limited improvement on propagated noise, but do reduce the leakage of these gates.…”

Section: Dynamic Gate Noise Reductionmentioning

confidence: 99%

Dynamic gates with hysteresis and configurable noise tolerance

Santhanam

Stevens

2007

2007 IFIP International Conference on Very Large Scale Integration

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Dynamic logic can provide significant performance and power benefit compared to implementations using static gates. Unfortunately dynamic gates have traditionally suffered from low noise margins, which limits their reliability. A new logic family, called complementary dynamic logic (CDL), is presented. CDL replaces the standard keeper logic with a dual dynamic keeper gate that is applicable to all dynamic gate structures. CDL provides dynamic gates with two novel characteristics: hysteresis and arbitrarily configurable noise margins. However, these two benefits come at the cost of reducing the gain and increasing the energy of the dynamic gate. This paper compares the noise, energy, performance, gain, and total transistor width tradeoffs of CDL and three other logic families applied to a 65nm cell library consisting of 23 functions. The results show that the performance advantages of dynamic domino gates can be maintained while providing significantly enhanced noise margins using CDL structures.

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Section: Dynamic Gate Noise Reductionmentioning

confidence: 99%

Dynamic gates with hysteresis and configurable noise tolerance

Santhanam

Stevens

2007

2007 IFIP International Conference on Very Large Scale Integration

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“…These noise metrics is widely implemented [7][8] [10]. For simulation purposes, we generate a noise pulse using a noise injection circuit (NIC) [2].…”

Section: Ante = E(v 2 Noise T Noise )mentioning

confidence: 99%

Noise tolerant low voltage XOR-XNOR for fast arithmetic

El-Gamel

Goel

Bayoumi

2003

Proceedings of the 13th ACM Great Lakes Symposium on VLSI

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With scaling down to deep submicron and nanometer technologies, noise immunity is becoming a metric of the same importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequency are the characteristics for deep submicron circuits. This paper proposes a low voltage noise tolerant XOR-XNOR gate with 8 transistors. The proposed gate has been implanted in an already existing (5-2) compressor cell to test its driving capability. The proposed gate is characterized and compared with those published ones for reliability and energy efficiency. The average noise threshold energy (ANTE) and the energy normalized ANTE metrics are used for quantifying the noise immunity and energy efficiency respectively. Results using 0.18µ CMOS technology and HSPICE for simulation show that the proposed XOR-XNOR circuit is more noise-immune and displays better power-delay product characteristics than the compared circuit. Also, the circuit proves to be faster in operation and works at all ranges of supply voltage starting from 0.6V to 3.3V.

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