A Novel Phase Frequency Detector for a High Frequency PLL Design

Majeed, Khaqan; Kailath, Binsu J

doi:10.1016/j.proeng.2013.09.110

Cited by 30 publications

(9 citation statements)

References 5 publications

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“…A PFD design using the pass transistor technology rather than the conventional CMOS transistors is proposed in [6]. The usage of pass transistors is mainly done since they ensure the operation at higher frequencies and also eliminates the reset path logic that is being used in the conventional CMOS circuit designs.…”

Section: Literature Reviewmentioning

confidence: 99%

Design and Implementation of Phase Frequency Detectors for Low-Power PLL

Bharadwaj¹,

Parashar²,

Dhanush³

et al. 2021

Lecture Notes in Electrical Engineering

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Section: Literature Reviewmentioning

confidence: 99%

Design and Implementation of Phase Frequency Detectors for Low-Power PLL

Bharadwaj¹,

Parashar²,

Dhanush³

et al. 2021

Lecture Notes in Electrical Engineering

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“…Phase frequency detectors (PFDs) are one of the important constituent blocks in the phase-locked loop (PLL) system, which plays a significant role in defining its lock time and reference spur. Traditionally linear PFDs (L-PFD) [1][2][3][4][5] have been used for the purpose; however, as they cause a lower gain, unwanted glitches, narrow loop BW, larger lock time and high reference spur, non-L-PFDs (NL-PFDs) have been proposed as a possible alternative [6][7][8]. NL-PFDs result in a higher-gain, wider-loop BW and smaller lock time for the PLL system.…”

Section: Introductionmentioning

confidence: 99%

PLL architecture with a composite PFD and variable loop filter

Majeed¹,

Kailath

2018

IET Circuits, Devices & Systems

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A novel phase-locked loop (PLL) architecture including a composite phase frequency detector (PFD), two charge pumps, variable loop filter topology and voltage-controlled oscillator is proposed in this study. Composite PFD offers higher-gain and loop bandwidth (BW) during tracking when Δϕ > π and provides a lower-gain and loop BW during tracking when Δϕ < π as well as after lock-in. The PLL system is designed to ensure stability by maximising and equalising phase margin in both the linear as well as non-linear operations. The transfer characteristics of composite PFD are free from the blind zone and also found possible to eliminate glitches from the output. A prototype of PLL operating at 2.56 GHz developed on 180 nm complementary metal-oxide-semiconductor process is found to achieve reference spur of −71.4 dBc, lock time of 2.05 μs, peak-to-peak jitter of 3.412 ps, phase noise of −110 dBc/Hz at 100 kHz and final placement area of 0.244 mm 2 .

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“…As the CL-PFD given in Fig. 1(a) cause dead zone, blind zone, lower gain, glitches at the output and associated large lock time and high reference spur [1,2], NL-PFDs have been proposed as a popular alternative [3,4,5]. Even though NL-PFDs offers higher gain, complicated design, complex circuits, presence of dead zone, blind zone and glitches at the output, all of these raise serious design constraints [4,5].…”

Section: Introductionmentioning

confidence: 99%

Nonlinear PFD free of glitches and blind zone for a fast locking PLL with reduced reference spur

Kuppalath

Kailath

2016

IEICE Electron. Express

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A simple nonlinear PFD circuit designed to achieve reduced reference spur and faster acquisition process for a PLL is proposed in this paper. The proposed nonlinear PFD is found to offer higher gain, eliminate glitches at the output and reduce both dead zone and reset delay when compared with the operation of conventional linear PFD (CL-PFD) and conventional NL-PFD (CNL-PFD). The PLL acquisition time got reduced by 50% and 11.69% while the reference spur 45% and 38.6% with respect to the CL-PFD and CNL-PFD respectively. Reference spur of −72.2 dBc, lock time of 1.548 µs, area of 0.2 mm 2 and power dissipation of 6.2 mW are obtained for the prototype PLL using Proposed NL-PFD designed with 180 nm CMOS process.

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A Novel Phase Frequency Detector for a High Frequency PLL Design

Cited by 30 publications

References 5 publications

Design and Implementation of Phase Frequency Detectors for Low-Power PLL

Design and Implementation of Phase Frequency Detectors for Low-Power PLL

PLL architecture with a composite PFD and variable loop filter

Nonlinear PFD free of glitches and blind zone for a fast locking PLL with reduced reference spur

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