A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET

Mukhopadhyay, Saibal; Mahmoodi, Hamid; Roy, Kaushik

doi:10.1109/tvlsi.2005.863743

Cited by 25 publications

(19 citation statements)

References 27 publications

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“…Conventional latch-based sense amplifiers can achieve less than 100 mV (10% of ) offset voltage. Wicht et al [43], discuss the yield and optimization of a latch type SRAM sense amplifier, and work in [44] extends that design to a double gated FinFET technology using independent gating. Fig.…”

Section: Architectural Considerationsmentioning

confidence: 99%

SRAM Read/Write Margin Enhancements Using FinFETs

Carlson

Guo

Balasubramanian

et al. 2010

IEEE Trans. VLSI Syst.

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Abstract-Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve control and reduce short channel effects. Among the likely candidates, FinFETs are the most attractive option because of their good scalability and possibilities for further SRAM performance and yield enhancement through independent gating. The enhancements to read/write margins and yield are investigated in detail for two cell designs employing independently gated FinFETs. It is shown that FinFET-based 6-T SRAM cells designed with pass-gate feedback (PGFB) achieve significant improvements in the cell read stability without area penalty. The write-ability of the cell can be improved through the use of pull-up write gating (PUWG) with a separate write word line (WWL). The benefits of these two approaches are complementary and additive, allowing for simultaneous read and write yield enhancements when the PGFB and PUWG designs are used in combination.

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Section: Architectural Considerationsmentioning

confidence: 99%

SRAM Read/Write Margin Enhancements Using FinFETs

Carlson

Guo

Balasubramanian

et al. 2010

IEEE Trans. VLSI Syst.

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“…Voltage latch sense amplifiers cannot reliably sense small signals, develops output signals slowly and severely limits radiation hardness in scaled devices [16]. The current latch sense amplifier called independent gate sense amplifier (IGSA) as shown in Fig.3 is reported by Mukhopadhyay et al [7]. And another current latch sense amplifier called radiation hardened independent gate sense amplifier (RHIGSA) as shown in Fig.4 is reported by Rathod et al [17].…”

Section: The Proposed Sense Amplifiermentioning

confidence: 99%

Low Power Double Gate Fin FET Based Sense Amplifier

Priyadarshni¹,

Singh²

2015

International Journal of Advanced Research in Computer and Comm

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Abstract:In this paper, a low power independent-gate, process variation tolerant double gate (DG) Fin FET based sense amplifier design has been proposed. As like RHIGSA, new design exploits the DICE (dual interlock cell) latch and the back gate of a double-gate Fin FET (DG Fin FET) device for dynamic compensation against process variation. But, there is change in tail transistor gate connections.,Which is dynamically controlled by intermediate signal in circuit. This design improves the power dissipation and show excellent tolerance to process parameter variations like temperature, V dd , thickness of oxide compared to Radiation hardend IGSA (RHIGSA) circuit and independent gate sense amplifier (IGSA). Proposed technique consumes 29.108% less power compare to RHIGSA.

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“…The circuit of Fig. 2(a) uses independently controlled gates which are investigated by simulated in [25][26][27][28] and their characteristic is shown in Fig. 2(b).…”

Section: Design Of Double-gate Mosfetmentioning

confidence: 99%

Analysis of double-gate CMOS for double-pole four-throw RF switch design at 45-nm technology

2011

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In this paper, we have analyzed a 45-nm RF CMOS switch design technology with the double-pole fourthrow circuit by using independently controlled double-gate MOSFET. The proposed switch reduces the number of transistors and increases the logic density per unit area as compare to the conventional CMOS switch. With the unique independent double-gate properties, we have demonstrated the potential advantages in terms of the drain current, threshold voltage, attenuation with ON resistance, flat-band capacitances, charge density and power dissipation of the proposed switch, which provides a switch with a significant drive circuit that is free from the signal propagation delay and additional voltage power supply. Moreover, the main emphasis is to provide a plurality of such switches arranged in a densely configured switch array, which provides a lesser attenuation, and better isolation with fast switching speed.

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A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET

Cited by 25 publications

References 27 publications

SRAM Read/Write Margin Enhancements Using FinFETs

SRAM Read/Write Margin Enhancements Using FinFETs

Low Power Double Gate Fin FET Based Sense Amplifier

Analysis of double-gate CMOS for double-pole four-throw RF switch design at 45-nm technology

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