2007 3rd Southern Conference on Programmable Logic 2007
DOI: 10.1109/spl.2007.371754 View full text |Buy / Rent full text
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Anna Antola,
Marco Domenico Santambrogio,
Marco Fracassi
et al.
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“…The columns in the table represent the following features: A) high-level (abstract) modeling and simulation; B) platform independence; C) code analyzability (i.e., semi-automated design-space exploitation); D) hardware code generation; E) software code generation; F) hardware/software co-design; G) supported target languages; H) open-source or free implementations; I) international standard. [15] VHDL Spark [29] VHDL 2 BlueSpec [49] C, Verilog Daedalus [65] C, C++, VHDL Koski [38] C, XML, VHDL PeaCE [31] C, C++, VHDL to achieve the goals of CTL, so it should not be considered as an exhaustive overview of all pros and cons of the solutions compared.…”
Section: Related Workmentioning
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“…The columns in the table represent the following features: A) high-level (abstract) modeling and simulation; B) platform independence; C) code analyzability (i.e., semi-automated design-space exploitation); D) hardware code generation; E) software code generation; F) hardware/software co-design; G) supported target languages; H) open-source or free implementations; I) international standard. [15] VHDL Spark [29] VHDL 2 BlueSpec [49] C, Verilog Daedalus [65] C, C++, VHDL Koski [38] C, XML, VHDL PeaCE [31] C, C++, VHDL to achieve the goals of CTL, so it should not be considered as an exhaustive overview of all pros and cons of the solutions compared.…”
Section: Related Workmentioning
“…Antola et al [4] performed tradeoff analysis using an Impulse-C/CoDeveloper-based framework that analyzed feasible PR-architectures based on execution time, inter-module communication interface bit-width, and resource usage. However, Impulse-C is proprietary, which inhibits portability/usability, and the partitioning methodology and tradeoff analysis details were not provided.…”
Section: Related Work and Contributionsmentioning
“…Currently frameworks capable of generating code from the same, ideally high-level specification, for both Hardware and Software synthesis are not available or presents severe limitations. C is one possible high level language as C to Gates tools and their corresponding design flows (ImpulseC [2], Handel-C [10] and Spark [7]) generate VHDL code from C-like specThis work is part of the ACTORS European Project (Adaptivity and Control of Resources in Embedded Systems), funded in part by the European Unions Seventh Framework Programme. Grant agreement no 216586 ifications.…”
Section: Introductionmentioning