A novel basis for logic rewriting

Abstract

Abstract-Given a set of logic primitives and a Boolean function, exact synthesis finds the optimum representation (e.g., depth or size) of the function in terms of the primitives. Due to its high computational complexity, the use of exact synthesis is limited to small networks. Some logic rewriting algorithms use exact synthesis to replace small subnetworks by their optimum representations. However, conventional approaches have two major drawbacks. First, their scalability is limited, as Boolean functions are enumerated to precompute their optimum representations. Second, the strategies used to replace subnetworks are not satisfactory. We show how the use of exact synthesis for logic rewriting can be improved. To this end, we propose a novel method that includes various improvements over conventional approaches: (i) we improve the subnetwork selection strategy, (ii) we show how enumeration can be avoided, allowing our method to scale to larger subnetworks, and (iii) we introduce XOR Majority Graphs (XMGs) as compact logic representations that make exact synthesis more efficient. We show a 45.8% geometric mean reduction (taken over size, depth, and switching activity), a 6.5% size reduction, and depth · size reductions of 8.6%, compared to the academic state-of-the-art. Finally, we outperform 3 over 9 of the best known size results for the EPFL benchmark suite, reducing size by up to 11.5% and depth up to 46.7%.

Logic Synthesis for Established and Emerging Computing

“…For example, AND-inverter graphs (AIGs), [41], [42] employ AND and inverters (or equivalently apply AND functions to positive/negative literals). Majority-inverter graphs (MIGs), [43] use majority and inverter gates and XOR-majority graphs (XMG) [44] use majority and EXOR gates. For FPGA design, bounded input lookup tables k-LUT networks are used, where ar(f ) ≤ k.…”

“…Examples of typical precomputed subnetworks are all four variables functions, or their 222 NPN equivalence classes [23], [44], [52]. Here, the idea is to replace four-input subnetworks with their optimum precomputed representation.…”

“…k-LUT mapping can be used as partition method of large networks in order to apply exact solutions on smaller functions of k inputs. Results of exact synthesis algorithm on LUT-mapped networks can be found in [44] to optimize size and in [26] to optimize logic depth.…”

Design automation and design space exploration for quantum computers

“…Multilevel representations are directed acyclic graphs called logic networks, in which terminal nodes are input variables or constants and internal nodes are logic operations. In the scope of this paper, we use And-inverter graphs (AIGs, [14]) and XORmajority graphs (XMGs, [15]) as logic networks. AIGs have AND gates and inverters as logic primitives and XMGs have XOR, majority-of-three, and inverters as logic primitives [15].…”

“…The same applies for the MAJ gate, if all of its operands are no longer required. We derive optimized XMGs from optimized AIGs using the algorithm presented in [15] using CirKit's 1 command 'xmglut -k 4' on AIGs that were optimized using multiple iterations of 'resyn2' in ABC.…”