1983
DOI: 10.1109/isscc.1983.1156498
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Abstract: A 1 . 5~ NMOS 16x16 PARALLEL MULTIPLIER designed for a throughput time of less than 40ns will be described. Preliminary measurements suggest a best-case throughput time of 16ns. The pipelined architecture of the multiplier ( Figure 1) gives a throughput time of one clock cycle and a total multiply time of two clock cycles. The chip draws 1W at LEV, has 7500 transistors, and dimensions of 2 8 0 0~ x 2 5 0 0~. It was designed to accept and deliver TTL logic levels. A photograph of the chip appears in Figure 2.T…

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