A new VDMOSFET structure with reduced reverse transfer capacitance

Sakai, T.; Murakami, Naoki

doi:10.1109/16.30945

Cited by 28 publications

(17 citation statements)

References 5 publications

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“…It is evident the electric field intensity of the proposed Fig. 3 The surface electric field distribution of the conventional, the device proposed in [5,6] and the proposed structure. structure is much lower than the presented before but closes to the conventional.…”

Section: The Results and Discussionmentioning

confidence: 96%

“…The R ON was tested by the Tektronix 371A under the conditions of I D = 6 A and V GS = 10 V. Fig. 3 shows the simulated electric field intensity near the surface of the conventional, the device proposed in [5,6] and the DGMOSFET with the pseudo-gate by ISE-TCAD [9]. It is evident the electric field intensity of the proposed Fig.…”

Section: The Results and Discussionmentioning

confidence: 99%

“…A thicker or a higher resistance epi-layer is used to maintain the V BR , leading to a higher R ON and higher conduction loss. Therefore, a floating p-region was added to eliminate the electric field concentration [5]. But it causes the rapid increase of R ON .…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Reducing the Gate Charge of Dual Gate Power VDMOSFET by Pseudo-Gate

Liao¹,

Chien²,

Lin³

et al. 2009

Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials

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Section: The Results and Discussionmentioning

confidence: 96%

Section: The Results and Discussionmentioning

confidence: 99%

See 1 more Smart Citation

Reducing the Gate Charge of Dual Gate Power VDMOSFET by Pseudo-Gate

Liao¹,

Chien²,

Lin³

et al. 2009

Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials

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“…SiC MOSFETs are being actively studied because of their superior switching characteristics compared to Si IGBTs [5,6]. To improve the switching characteristics of SiC MOSFETs, the gate-drain capacitance (C GD ) must be reduced because switching power loss occurs mainly during the charging and discharging of the C GD [7]. A well-known method to reduce the C GD is a split-gate MOSFET [8].…”

Section: Introductionmentioning

confidence: 99%

A 1.2 kV SiC MOSFET with Integrated Heterojunction Diode and P-shield Region

Yoon

Kim

2021

Energies

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A 1.2 kV SiC MOSFET with an integrated heterojunction diode and p-shield region (IHP-MOSFET) was proposed and compared to a conventional SiC MOSFET (C-MOSFET) using numerical TCAD simulation. Due to the heterojunction diode (HJD) located at the mesa region, the reverse recovery time and reverse recovery charge of the IHP-MOSFET decreased by 62.5% and 85.7%, respectively. In addition, a high breakdown voltage (BV) and low maximum oxide electric field (EMOX) could be achieved in the IHP-MOSFET by introducing a p-shield region (PSR) that effectively disperses the electric field in the off-state. The proposed device also exhibited 3.9 times lower gate-to-drain capacitance (CGD) than the C-MOSFET due to the split-gate structure and grounded PSR. As a result, the IHP-MOSFET had electrically excellent static and dynamic characteristics, and the Baliga’s figure of merit (BFOM) and high frequency figure of merit (HFFOM) were increased by 37.1% and 72.3%, respectively. Finally, the switching energy loss was decreased by 59.5% compared to the C-MOSFET.

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“…Therefore, a thicker or a higher resistance epi-layer is needed to maintain breakdown voltage, but a high R ON and high conduction loss occur at the same time. Consequently, a floating p-region was added between the DG structure to relax the electric field crowding effect 13 . However, the added floating p-region causes the R ON to increase rapidly.…”

mentioning

confidence: 99%