In this paper, we propose a fast arithmetic error feedback (EF) structure with shift operation circuits and shared multiplier. For optimization of EF network, we show the design method based on the Lagrange multiplier method for designing the shared multiplier and the branch and bound based algorithm for optimization of the shift operation circuits. The branch and bound method can reduce the calculation cost because the sub-trees can be cut based on the lower bound estimation. Finally, we present a numerical example by designing the EF with shift operation circuits and shared multiplier. From the results, we demonstrate the effectiveness of the proposed method and show the calculation time is a few seconds.
I. INTRODUCTIONWhen realizing a digital filters with fixed point arithmetic in the finite word-length hardware, as known from Figures 1, 2B bits multiplied data must be quantized to B bits data before the next multiplication. Then an error e(n) due to product roundoff occurs as shown in Figure 1 and it appears at the filter output as a roundoff noise.The error feedback (EF) has been studied as the reduction method of the roundoff noise [1]-[6]. EF can be used in many kinds of filter structures (e.g. transfer function model[3], [4], [6], cascade form[2] and local state-space model[1], [4], [5]) and never change the filter transfer function. If the digital filter is described a rational transfer function, it is hard to synthesize the low roundoff noise structure unlike the local state space model. So such a case is particularly convenience to use the EF for reduction of the roundoff noise. Figure 2 shows IIR digital filters (Direct-Form II implementation) with EF network. In hardware, the word-length of EF coefficients are finite and short word-length realization is better from cost point of view. So the design method for finite word-length EF coefficients is proposed based on the branch and bound principle [7], [8].In this paper, we propose a fast arithmetic EF described by a rational transfer function. The EF structure consists shift operation circuits and shared multiplier. This problem is a kind of the discrete combination problem, so it is difficult to find the best solution. To solve this problem, we show the method to search for the best solution in a short time. The algorithm is based on the lower-bound estimation principle using the relaxation problem and the shift operation circuits of EF designed by the method have guaranteed optimality. The relaxation solution can be calculated by the Lagrange multiplier method.In numerical example, we design the optimal and proposed EF under a specified condition. The performance of the proposed EF is