A New Real-Time Lucky Imaging Algorithm and its Implementation Techniques

Abstract

Lucky imaging is a high-angular resolution astronomical image reconstruction technique that can effectively reduce the impact of atmospheric turbulence on image quality and improve the imaging resolution of ground-based telescopes. Its key steps include image selection, registration and superposition. However, the lucky imaging algorithms based on a central processing unit (CPU) encounter difficulty accomplishing real-time processing; thus, they are post-processing methods and cannot meet the needs of on-site observers. Taking advantage of the parallelism and flexibility of the field programmable gate array (FPGA), this paper presents a new real-time lucky imaging algorithm that features real-time processing and dynamic updating and displaying. The algorithm consists of a dynamic sorting-free image selection algorithm, an improved registration and storage method, a parallel superposition algorithm, a parallel preprocessing method for noise suppression and cosmic ray removal, and a dynamic multithreshold display scheme. The simulation results show that the algorithm is feasible, effective and efficient. Compared with other lucky imaging algorithms based on FPGAs, this algorithm shows great advantages in clock consumption and on-chip resource consumption. Furthermore, it can be implemented on a small or medium-size development board of an FPGA. Moreover, the implemented FPGA system can perform real-time and dynamic lucky imaging for more than 10,000 frames of short-exposure images with an original format of 512 × 512 pixels continuously. The experimental results not only show the validity of the proposed algorithm but also demonstrate the feasibility of the proposed implementation techniques for the FPGA-based algorithm.INDEX TERMS Astronomical observation, data reduction, FPGA, lucky imaging, real-time processing.

On-the-Fly Parallel Processing IP-Core for Image Blur Detection, Compression, and Chaotic Encryption Based on FPGA

“…The FPGAs are used in many applications, such as the PRNG [12], Neural Networks [29], encryption [30], edge detection [31], and compression [32]. In the past decade, the FPGAs have been used in the field of image processing due to their powerful parallel processing capabilities [33]. They can exploit the temporal and spatial parallelism of many image processing algorithms.…”

A novel hybrid algorithm for lucky imaging

“…This problem is more remarkable in LF algorithm. Therefore, considering that the sequence of selection results has no impact on subsequent operations, this paper adopts the idea of real-time image selection in image space based on comparison but no sorting as proposed in Wang et al (2020) to design applicable selection and storage schemes for LI and LF algorithms which can greatly save computer memory.…”

“…But this method suffers two drawbacks: the size of the central low spatial frequency patch is selected by trial and error, and the imaging effect is dependent on the patch and the given selection percentages. In 2018, Mao et al subjected the conventional lucky imaging algorithm to partial graphics processing unit (GPU) acceleration (Mao et al 2018)while Zhao et al (Zhao et al 2019)used field programmable gate array (FPGA) for experimental study of the lucky imaging algorithm; in 2019, Hu et al (Hu 2019)carried out experimental study of packet processing of the LF algorithm on an observation system without AO; and in 2020, Wang et al (Wang et al 2020)modified the conventional lucky imaging algorithm, proposed a algorithm where real-time processing is possible, and carried out on a FPGA system the corresponding experimental study.…”

“…and Wang et al (2020) modified the conventional lucky imaging algorithm, proposed an algorithm where real-time processing is possible, and carried out on an FPGA system the corresponding experimental study.…”

An FPGA-Based Hardware Accelerator for Real-Time Block-Matching and 3D Filtering

“…For instance, a modern GPU device normally consumes more than 250W power [11], which is infeasible for embedded application scenarios, such as robotics, autonomous vehicles and surveillance systems. On the other hand, fieldprogrammable gate array devices (FPGAs), which provide massive processing elements, reconfigurable interconnections and lower power dissipation, are naturally suitable to implement compute-intensive image processing algorithms [1], [12]- [15]. For instance, our previous study of [17] has presented an FPGA-based BM3D accelerator design which achieved 12× speed-up over the OpenCL-based GPU implementation of [8].…”