A New Power-Gated Hybrid Defect Tolerant Approach Based on Modular Redundancy

Pal, Soumyaranjan; Mukherjee, Atin

doi:10.1109/asiancon51346.2021.9544937

Cited by 2 publications

(1 citation statement)

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“…In that suggested future work, redundancy should be explored along with pipelining and lightweight architectures, to carry out research concerning the different design and implementation parameters, as well as to explain the behavior due to the combination of these techniques. Besides, we will focus on reducing power-draining by considering the idea developed by Pal and Mukherjee in [27]. They proposed a logic that when there was no fault in the system, instead of activating all of the modules, they only activated two of them.…”

Section: Future Workmentioning

confidence: 99%

A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors

Algredo‐Badillo

Morales-Sandoval

Medina-Santiago

et al. 2022

Sensors

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In emergent technologies, data integrity is critical for message-passing communications, where security measures and validations must be considered to prevent the entrance of invalid data, detect errors in transmissions, and prevent data loss. The SHA-256 algorithm is used to tackle these requirements. Current hardware architecture works present issues regarding real-time balance among processing, efficiency and cost, because some of them introduce significant critical paths. Besides, the SHA-256 algorithm itself considers no verification mechanisms for internal calculations and failure prevention. Hardware implementations can be affected by diverse problems, ranging from physical phenomena to interference or faults inherent to data spectra. Previous works have mainly addressed this problem through three kinds of redundancy: information, hardware, or time. To the best of our knowledge, pipelining has not been previously used to perform different hash calculations with a redundancy topic. Therefore, in this work, we present a novel hybrid architecture, implemented on a 3-stage pipeline structure, which is traditionally used to improve performance by simultaneously processing several blocks; instead, we propose using a pipeline technique for implementing hardware and time redundancies, analyzing hardware resources and performance to balance the critical path. We have improved performance at a certain clock speed, defining a data flow transformation in several sequential phases. Our architecture reported a throughput of 441.72 Mbps and 2255 LUTs, and presented an efficiency of 195.8 Kbps/LUT.

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Section: Future Workmentioning

confidence: 99%