A multiple valued logic: a tutorial and appreciation

Smith, K.C.

doi:10.1109/2.48

Cited by 173 publications

(66 citation statements)

References 7 publications

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“…In the first ex periment, we use Fig. 7(a) as the teacher's signals and show how the learning can shift the literal window from x1(0,0) to x1 (2,2). Simulation shows that the system learned to shift it to the correct place x1(2, 2), as shown in Fig.…”

Section: Simulation Resultsmentioning

confidence: 99%

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A Learning Multiple-Valued Logic Network that can Explain Reasoning

1999

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This paper describes a learning multiple-valued logic (MVL) network that can explain reasoning. The learning MVL network is derived directly from a canonical realization of MVL functions and therefore its functional completeness is guaranteed. We develop traditional back-propagation to the MVL networks and drive a specific algorithm for the MVL networks. The algorithm combines back-propagation learning with other features of MVL networks, including the prior human knowledge on the MVL networks, for example, the rchitecture, the number of hidden units and layers, and many other useful parameters for the networks. The prior knowledge from the MVL canonical form can be used as initial parameters of the learning MVL network in its learning process. As a result, the prior knowledge can guide the back-propagation learning process to get started from a point in the parameter space that is not far from the optimal one, thus, back-propagation can fine-tune the prior knowledge for achieving a desired output easily. This cooperative relation between the prior knowledge and the back-propagation learning process is not always present in neural networks. The learning process in the MVL network also shares some cytology behaviors, in particular the cell adhesion, the cell aptopsis (the death of cell), and the cluster cell aptopsis (the death of cluster cells), and presents these properties in the artificial MVL network successfully. Simulation results are also given to confirm the effectiveness of the methods.

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Section: Simulation Resultsmentioning

confidence: 99%

“…Besides reductions in interconnection and chip area, multiple-valued logic (MVL) networks have emerged as powerful image processing [1] and speech recognition [2] techniques. However, these networks cannot learn or adapt to gradual change in their environments.…”

Section: Introductionmentioning

confidence: 99%

A Learning Multiple-Valued Logic Network that can Explain Reasoning

1999

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“…The increased data density due to the higher informational content per conductor is one of the main benefits of MVL circuit implementations [1][2][3]. Several transistor-based implementation technologies have been proposed to realize MVL circuits [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. Conventional electronic MVL circuits can be categorized as currentmode, voltage-mode, or mixed-mode circuits.…”

Section: Introductionmentioning

confidence: 99%

Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits

Datla

Thornton

2010

2010 40th IEEE International Symposium on Multiple-Valued Logic

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“…the decimal number 255 is represented as 1111 1111 in binary and 3333 in quaternary. As the circuits become less complicated, the data processing may be fast and reliable [2,3]. However, multi-valued logic designs may be challenging due to difficulties in implementation [4].…”

Section: Introductionmentioning

confidence: 99%

Design of High Performance Quaternary Adders

S¹,

Gurumurthy²

2010

IJCTE

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Abstract-Design of the binary logic circuits is limited by the requirement of the interconnections. A possible solution could be arrived at by using a larger set of signals over the same chip area. Multiple-valued logic (MVL) designs are gaining importance from that perspective. This paper presents two types of multiple-valued full adder circuits, implemented in Multiple-Valued voltage-Mode Logic (MV-VML). First type is designed using one hot encoding and barrel shifter. Second full adder circuit is designed by converting the quaternary logic in to unique code, which enables to implement circuit with reduced hard ware. Sum and carry are processed in two separate blocks, controlled by code generator unit. The design is targeted for the 0.18 µm CMOS technology and verification of the design is done through Synopsis HSPICE and COSMOSCOPE Tools. Area of the designed circuits is less than the corresponding binary circuits and quaternary adders because number of transistors used are less.Keywords-Down literal circuit, multi-level logic, quaternary full adder, One hot encoding.

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A multiple valued logic: a tutorial and appreciation

Cited by 173 publications

References 7 publications

A Learning Multiple-Valued Logic Network that can Explain Reasoning

A Learning Multiple-Valued Logic Network that can Explain Reasoning

Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits

Design of High Performance Quaternary Adders

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