A Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance Systems

Kim, Daehyeok; Song, Minkyu; Choe, Byeongseong; Kim, Soo Youn

doi:10.3390/s17071497

Cited by 18 publications

(13 citation statements)

References 12 publications

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“…In the future, the proposed content-driven approach will be suitable for intelligent surveillance with multiresolution image sensors. (21) More specifically, the salient objects can be well sampled in a high-resolution mode with more pixels by sampling the backgrounds with fewer pixels.…”

Section: Resultsmentioning

confidence: 99%

Image Resizing in Saliency Histogram Domain

2017

Sensors and Materials

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The saliency map of an image provides useful information regarding the region of interest. In this paper, the normalized saliency map, called the saliency histogram, is used as a valid probability density function, based on which an efficient algorithm has been proposed for image resizing in the saliency histogram domain. Moreover, the saliency-histogram-based image resizing algorithm has been extended to video applications. Experimental results show the performance of the saliency histogram in terms of the preservation of salient objects in resized images and videos. The proposed approach is suitable for content-driven surveillance with multiresolution image sensor systems.

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Section: Resultsmentioning

confidence: 99%

Image Resizing in Saliency Histogram Domain

2017

Sensors and Materials

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“…To overcome the low-speed problem, multiple two-step (TS) SS ADCs have been proposed [12][13][14][15][16][17][18][19][20][21]. A T-bit TS SS ADCs divide the A/D conversion process into M-bit coarse conversion and N-bit fine conversion where T = M＋N.…”

Section: Introductionmentioning

confidence: 99%

A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors

Zhang

Ning

et al. 2020

IEEE Access

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This paper proposes a novel 12-bit column-parallel two-step single-slope (SS) analog-todigital converter (ADC) for high-speed CMOS image sensors. Cooperating with the output offset storage (OOS) technique, a new correlated double sampling (CDS) is adopted to reduce the non-uniformity in column-level ADCs. In the proposed structure, the decision point of the comparator is independent of the input signal. The variation of the comparator offset caused by the input level is eliminated. Through a foreground calibration, the non-idealities from the ramp generator and the column ADC are both corrected. Design and simulation in a 130nm CMOS process, the proposed ADC achieves the differential nonlinearity (DNL) of +0.76/-0.8 LSB and the integral nonlinearity (INL) of +1.06/-0.84 LSB at a sampling frequency of 100 KS/s with the calibration. The effective number of bits (ENOB) is also improved from 4.66 bits to 11.25 bits. The single ADC occupies an active area of 7.5×775 μm 2 and the power consumption is 72 μW. INDEX TERMS Column-parallel ADC; single-slope (SS) ADC; two-step ADC; foreground calibration

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“…Complementary Metal-Oxide-Semiconductor (CMOS) [1] has been attracting attentions due to its high sensitivity and low cost. However, CMOS sensor encounters inevitably some problems like illumination and motion blurred when it captures images.…”

Section: Introductionmentioning

confidence: 99%

A Sensor Image Super-Resolution via Advanced Generative Adversarial Network

Wang¹,

He²,

Du-yan³

et al. 2018

Preprint

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Complementary Metal-Oxide-Semiconductor (CMOS) is a typical image sensor that has a wide range of applications. However, considering the limitations of the weather condition and hardware cost, it is hard to capture high-resolution images by CMOS sensor. Recently, Super-Resolution (SR) techniques for image restoration has been gaining attentions due to its excellent performance. Under the powerful learning ability, Generative Adversarial Networks (GANs) have been proved to achieve great success. In this paper, we propose the Advanced Generative Adversarial Networks (AGAN) to efficiently correct these issues; 1) we design a Laplacian pyramid framework as pre-trained module, which is beneficial to provide multi-scale features for our input. 2) at each feature block, a convolutional skip-connections network, which may contain some latent information, is significant for generative model to reconstruct a plausible-looking image; 3) considering that edge details usually play an important role in image generation, a novel perceptual loss function is defined to train and seek optimal parameters. It is effective to achieve excellent and compelling quality captured by CMOS sensor. Quantitative and qualitative evaluations have been demonstrated that our algorithm not only fully takes advantage of Convolutional Neural Networks (CNNs) to improve the image quality, but also performs better than previous GAN algorithms for super-resolution task.

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A Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance Systems

Cited by 18 publications

References 12 publications

Image Resizing in Saliency Histogram Domain

Image Resizing in Saliency Histogram Domain

A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors

A Sensor Image Super-Resolution via Advanced Generative Adversarial Network

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