A monolithic digital clock-generator for on-chip clocking of custom DSP's

Abstract

This work shows a robust and easily implemented clock generator for custom designs. It is a fully digital design suitable for both high-speed clocking and low-voltage applications. This clocking method is digital, and it avoids analog methods like phase locked loops or delay line loops. Instead, the clock generator is based on a ring counter which stops a ring oscillator after the correct number of cycles. Both a 385 MHz clock and a 15 MHz custom DSP application using the onchip clocking strategy are described. The prototypes have been fabricated in a 0.8 pm standard CMOS process. The major advantages with this clocking method are robustness, small size, low-power consumption, and that it can operate at a very low supply voltage.

Demystifying Data-Driven and Pausible Clocking Schemes

“…Pěchouček also outlines a data-driven clocking scheme where the generation of a fixed number of clock cycles is triggered by the arrival of input data. This type of clocking scheme was more recently employed to create an on-chip clock generator for a DSP [25] and a data-driven GALS clocking scheme for a low-power reconfigurable processor [36]. There are no synchronisation issues with such a scheme as the clock is always quiescent when the initial asynchronous data input arrives.…”

SSTL IO Standard Based Energy Efficient Digital Clock Design on 28nm FPGA

“…A digital clock design which is based on Nios has also been introduced [2]. Digital designs are suitable for both high-speed clocking and low-voltage applications [3]. Digital methods avoids phase loops or delay line loop which are referred to as analog methods [3].…”

“…Digital designs are suitable for both high-speed clocking and low-voltage applications [3]. Digital methods avoids phase loops or delay line loop which are referred to as analog methods [3]. The objective of this design is to minimize system's dynamic power consumption [4].…”

A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

“…In order to have a good linear tuning range, the width of the transistor M1 has to be increased as illustrated in (7). Consequently the equivalent resistance R1 will decrease, resulting in a smaller delay tuning range.…”

“…With the increasing performance and decreasing cost of digital VLSI design technology, all digital phase-locked loops have become more attractive. Although ADPLL will not have the same performance as its analog counterpart, it provides a faster lock-in time and better testability, stability, and portability over difference process [6,7].…”