A modified Costas loop for clock recovery and frequency synthesis

Amourah, M.M.; Geiger, R.L.

doi:10.1109/iscas.1998.704232

Cited by 4 publications

(2 citation statements)

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“…The VCO .is constructed using differential delay cells. The lowpass filters and the subtractor are realized with a charge pump driving a charge storage capacitor in the loop filter[20]. An input sampler is used to allow us to deal with both RZ and NRZ binary input and to pinch the input transitions to the detector between the transitions of the leading and the lagging outputs from the oscillator.…”

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A high speed data recovery circuit with lead/lag phase detection

Amourah¹

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A Phase/Frequency Detector (PFD) that has a simple structure and a fast response is presented. This PFD has three signal inputs and no dead zone. The absence of the dead zone reduces an important component of the jitter. An implementation .of this PFD in a clock recovery circuit is also presented. A data recovery architecture that uses this fast clock recovery circuit is described. A clock recovery circuit that operates at 1GHz in a 0.6u CMOS N-Well process is discussed.

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“…Finally we subtract these two error signals to provide the control voltage for the VCO. If we have an input signal Xin = Vin cos(cvint+eiJ, and a sinusoidal oscillator output V1o cos( cv 10 t + 0 10 ); then it can be shown from a simple manipulation of trigonometric identities that the error signal e, (the VCO control voltage), will be[20]…”

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confidence: 99%