A Mismatch-Immune 12-Bit SAR ADC With Completely Reconfigurable Capacitor DAC

Collins, Nicholas R.; Tamez, Andres; Lü, Jie; Pernillo, Jorge; Flynn, Michael P.

doi:10.1109/tcsii.2017.2775243

Cited by 2 publications

(1 citation statement)

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“…Design different switching strategies to reduce quantization error and power consumption [11]. Engineers and researchers do much research and work about digital calibration techniques to improve the capacitor mismatch [12]. Each of these structures has its advantages, mainly depending on the requirements of the application domain.…”

Section: Introductionmentioning

confidence: 99%

Low Power SAR ADC Design with Digital Background Calibration Algorithm

Chen

Liang

et al. 2020

Symmetry

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This paper proposed a digital background calibration algorithm with positive and negative symmetry error tolerance to remedy the capacitor mismatch for successive approximation register analog-to-digital converters (SAR ADCs). Compensate for the errors caused by capacitor mismatches and improve the ADC performance. Combination with a tri-level switching scheme based on the common-mode voltage Vcm to achieve capacitor reduction and high switching energy efficiency. The proposed calibration algorithm significantly improves capacitor mismatch without resorting to extensive computation or dedicated circuits. The active area is 0.046 mm2 in 40 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The post-simulation results show the effective number of bits (ENOB) improves from 8.23 bits to 11.36 bits, signal-to-noise-and distortion ratio (SNDR) improves from 51.33 dB to 70.15 dB, respectively, before and after calibration. This improves the spurious-free dynamic range (SFDR) by 24.13 dB, from 61.50 dB up to 85.63 dB. The whole ADC’s power consumption is only 0.3564 mW at sampling rate fs =2 MS/s and Nyquist input frequency, with a figure-of-merit (FOM) 67.8 fJ/conv.-step.

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Section: Introductionmentioning

confidence: 99%