A method for register allocation to loops in multiple register file architectures

Kolson, David J.; Nicolau, Alexandru; Dutt, Nikil; Kennedy, Ken

doi:10.1109/ipps.1996.508035

Cited by 4 publications

(4 citation statements)

References 20 publications

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“…In particular, ParShield has no performance impact and little area requirements. Kolson et al [6] proposed a register allocation architecture to loop in multiple register files, where the available registers have been partitioned into multiple banks. A distinguishing characteristic of the approach is that the register assignment may span multiple iterations of the original loop.…”

Section: Related Workmentioning

confidence: 99%

Balanced Bipartite Graph Based Register Allocation for Network Processors in Mobile and Wireless Networks

Tang

You

Guo

et al. 2010

Mobile Information Systems

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Mobile and wireless networks are the integrant infrastructure of mobile and pervasive computing that aims at providing transparent and preferred information and services for people anytime anywhere. In such environments, end-to-end network bandwidth is crucial to improve user's transparent experience when providing on-demand services such as mobile video playing. As a result, powerful computing power is required for networked nodes, especially for routers. General-purpose processors cannot meet such requirements due to their limited processing ability, and poor programmability and scalability. Intel's network processor IXP is specially designed for fast packet processing to achieve a broad bandwidth. IXP provides a large number of registers to reduce the number of memory accesses. Registers in an IXP are physically partitioned as two banks so that two source operands in an instruction have to come from the two banks respectively, which makes the IXP register allocation tricky and different from conventional ones. In this paper, we investigate an approach for efficiently generating balanced bipartite graph and register allocation algorithms for the dual-bank register allocation in IXPs. The paper presents a graph uniform 2-way partition algorithm (FPT), which provides an optimal solution to the graph partition, and a heuristic algorithm for generating balanced bipartite graph. Finally, we design a framework for IXP register allocation. Experimental results demonstrate the framework and the algorithms are efficient in register allocation for IXP network processors.

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Section: Related Workmentioning

confidence: 99%

Balanced Bipartite Graph Based Register Allocation for Network Processors in Mobile and Wireless Networks

Tang

You

Guo

et al. 2010

Mobile Information Systems

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“…Kolson, A. Nicolau, N. Dutt et al presented a method for register allocation in loops minimizing spilling in multiple RF architectures [29]. Their solution exhaustively tries all possible register assignments for the live variables within the loop body.…”

Section: Related Workmentioning

confidence: 99%

Cluster assignment of global values for clustered VLIW processors

Terechko

Thénaff

Corporaal

2003

Proceedings of the 2003 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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In this paper high-level language (HLL) variables that are alive in a whole HLL function, across multiple scheduling units, are termed as global values. Due to their long live ranges and, hence, large impact on the schedule, the global values require different compiler optimizations than local values, which span across only one scheduling unit. The instruction scheduler for a clustered ILP processor, which is responsible for cluster assignment of operations and variables, faces a difficult problem of assigning global values to clusters. Our study shows that trivial assignments (e.g. mapping all global values into one cluster) may result in a severe cycle count overhead relative to the unicluster of up to 26.3% for a four cluster VLIW machine. This paper presents three advanced algorithms for assigning global values to clusters based on multi-pass scheduling and affinity of variables. Furthermore, we measure performance of these algorithms on optimized multimedia C applications and assess quality of our algorithms by comparing them to a practical higher performance bound derived from a vast random search. Our algorithms reduce the execution time overhead of the best simple algorithm round-robin from 10.5% to 5.9% for the two cluster VLIW machine and from 17.3% to 14.12% for the four cluster VLIW machine.

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“…As an example case, the proposed method is applied on transport triggered architecture (TTA) processor [8] [9]. On the contrary to register assignment techniques targeted directly for partitioned RFs [10], our approach is to have RF mapping as an extra step after the register assignment. The compiler can assume monolithic RF with unlimited number of ports which is convenient if a simple compiler is used.…”

Section: Introductionmentioning

confidence: 99%

“…This mapping of registers to RFs is studied in this paper. Register assignment to multiple RFs in loops is studied in [10]. In our approach, the initial assignment of intermediate values to symbolic registers remains untouched.…”

Section: Introductionmentioning

confidence: 99%

Register File Partitioning with Constraint Programming

Salmela

Shen

Bhattacharyya

et al. 2006

2006 International Symposium on System-on-Chip

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Highly parallel processors call for high bandwidth register access. One solution is to use multi-port register files. However, such register files are expensive in terms of chip area and their access time can lower the maximum clock frequency of the processor. Therefore, partitioning the multi-port register file to several smaller register files with less ports is preferred. In this paper, the partitioning of the register file is studied and the problem is formalized into such a form that constraint programming paradigm can be used to search for applicable register file partitionings. With the aid of the proposed method, applicable register file partitions with no performance penalty can be found and the inherent drawbacks of multi-port register file can be avoided.

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A method for register allocation to loops in multiple register file architectures

Cited by 4 publications

References 20 publications

Balanced Bipartite Graph Based Register Allocation for Network Processors in Mobile and Wireless Networks

Balanced Bipartite Graph Based Register Allocation for Network Processors in Mobile and Wireless Networks

Cluster assignment of global values for clustered VLIW processors

Register File Partitioning with Constraint Programming

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