A mechanistic performance model for superscalar out-of-order processors

Abstract

A mechanistic model for out-of-order superscalar processors is developed and then applied to the study of microarchitecture resource scaling. The model divides execution time into intervals separated by disruptive miss events such as branch mispredictions and cache misses. Each type of miss event results in characterizable performance behavior for the execution time interval. By considering an interval's type and length (measured in instructions), execution time can be predicted for the interval. Overall execution time is then determined by aggregating the execution time over all intervals. The mechanistic model provides several advantages over prior modeling approaches, and, when estimating performance, it differs from detailed simulation of a 4-wide out-of-order processor by an average of 7%. The mechanistic model is applied to the general problem of resource scaling in out-of-order superscalar processors. First, we use the model to determine size relationships among microarchitecture structures in a balanced processor design. Second, we use the mechanistic model to study scaling of both pipeline depth and width in balanced processor designs. We corroborate previous results in this area and provide new results. For example, we show that at optimal design points, the pipeline depth times the square root of the processor width is nearly constant. Finally, we consider the behavior of unbalanced, overprovisioned processor designs based on insight gained from the mechanistic model. We show that in certain situations an overprovisioned processor may lead to improved overall performance. Designs where a processor's dispatch width is wider than its issue width are of particular interest

A mechanistic performance model for superscalar in-order processors

“…The in-order CPI stacks are obtained using the model described in this paper; the out-of-order CPI stacks are obtained using the model described in prior work [8]. In this comparison, we consider four-wide inorder and out-of-order processors.…”

“…Taha and Wills [28] propose a mechanistic model that breaks up the execution into so-called macro blocks, separated by miss events. Eyerman et al [8] propose the interval model for superscalar out-of-order processors. Whereas all of this prior work focused on out-of-order processors, Breughe et al [3] proposed a mechanistic model for scalar in-order processors.…”

“…Whereas prior work in analytical performance modeling has focused on superscalar out-of-order processors [8,17], in this paper we propose a mechanistic model for superscalar in-order processors. Counterintuitively perhaps, inorder processor performance is more complicated to model than out-of-order processor performance using a mechanistic model.…”

“…Interval analysis, which is a mechanistic model for su- perscalar out-of-order processors [8,17], was based on the observation that in the absence of miss events such as cache misses and branch mispredictions, a well-balanced superscalar out-of-order processor can smoothly stream instructions through its pipelines, buffers and functional units. Under ideal conditions the processor sustains a level of performance (instructions per cycle) roughly equal to the width of the processor.…”

Cache Pirating: Measuring the Curse of the Shared Cache

“…To address this, a substantial amount of work has been done to improve simulation performance [12,16,21]. In particular, accuracy and detail can be traded for performance by the use of analytical performance models [18,22].…”