A low power radix-4 dual recoded integer squaring implementation for use in design of application specific arithmetic circuits

Abstract

Abstract:We introduce an implementation of a radix 4 dual recoding procedure for the squaring operation of an n-bit number which reduces the number of bit product terms employed in the previously known squaring methods obtained by either Booth radix-4 recoded multiplication or by radix 2 squaring. Several other squaring algorithms have been developed such as [WSMB99], [YW01], and [SNC01]. Employing the dual recoded radix-4 procedure for design of a squaring circuit introduces a significant reduction in power and area. Architecturally, radix-4 dual recoded squaring uses only the 1's complement representation which allows for a simpler PPG structure as compared to the 2's complement representation required for Booth radix-4 multiplication.

A Low Power High Performance Radix-4 Approximate Squaring Circuit

“…The Booth-folded recoded squarer in [16] reduces two's complementation to a straightforward one's complementation. Avoidance of two's complementation particularly simplifies the generation of integer squares modulo the integer word size, as further investigated in [22]. In this paper, we investigate implementations of a new radix-4 operand dual recoding method [5] for the squaring operation.…”