A Low-Power Multithreaded Processor for Baseband Communication Systems

Schulte, Michael; Glossner, CJ; Mamidi, Suman; Moudgill, Mayan; Vassiliadis, S.

doi:10.1007/978-3-540-27776-7_41

Cited by 13 publications

(16 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Examples of these devices include recent generations of FPGAs are now including dedicated DSP slices and complete processor cores, but are programmed using traditional FPGA design tools. Another example is the Sandbridge Sandblaster processor which contains multiple DSP cores and an ARM9 processor, and is treated as a DSP device [28]. Future SDR platforms will likely take advantage of this trend to deliver increased capacity, with the likelihood of the increasingly complex FPGAs being utilized first due to their relative maturity.…”

Section: Diverse Range Of Processorsmentioning

confidence: 99%

Software-Defined Radio Demonstrators: An Example and Future Trends

Farrell

Sánchez

Corley

2009

International Journal of Digital Multimedia Broadcasting

View full text Add to dashboard Cite

Software-defined radio requires the combination of software-based signal processing and the enabling hardware components. In this paper, we present an overview of the criteria for such platforms and the current state of development and future trends in this area. This paper will also provide details of a high-performance flexible radio platform called the maynooth adaptable radio system (MARS) that was developed to explore the use of software-defined radio concepts in the provision of infrastructure elements in a telecommunications application, such as mobile phone basestations or multimedia broadcasters.

show abstract

Section: Diverse Range Of Processorsmentioning

confidence: 99%

Software-Defined Radio Demonstrators: An Example and Future Trends

Farrell

Sánchez

Corley

2009

International Journal of Digital Multimedia Broadcasting

View full text Add to dashboard Cite

show abstract

“…Multiple copies (e.g., banks and/or modules) of memory are available for each thread to access. The Sandblaster processor uses the Token Triggered Threading (T 3 ) form of interleaved multithreading, 13 in which each thread is allowed to simultaneously execute an instruction, but only one thread may issue an instruction on a cycle boundary. The microarchitecture currently supports up to eight concurrent hardware threads.…”

Section: Sandbridge Multithreadingmentioning

confidence: 99%

Software-based geometry operations for 3D computer graphics

Sima

Iancu²,

Glossner

et al. 2006

SPIE Proceedings

Self Cite

View full text Add to dashboard Cite

In order to support a broad dynamic range and a high degree of precision, many of 3D renderings fundamental algorithms have been traditionally performed in floating-point. However, fixed-point data representation is preferable over floatingpoint representation in graphics applications on embedded devices where performance is of paramount importance, while the dynamic range and precision requirements are limited due to the small display sizes (current PDA's are 640 × 480 (VGA), while cell-phones are even smaller). In this paper we analyze the efficiency of a CORDIC-augmented Sandbridge processor when implementing a vertex processor in software using fixed-point arithmetic. A CORDIC-based solution for vertex processing exhibits a number of advantages over classical Multiply-and-Acumulate solutions. First, since a single primitive is used to describe the computation, the code can easily be vectorized and multithreaded, and thus fits the major Sandbridge architectural features. Second, since a CORDIC iteration consists of only a shift operation followed by an addition, the computation may be deeply pipelined. Initially, we outline the Sandbridge architecture extension which encompasses a CORDIC functional unit and the associated instructions. Then, we consider rigid-body rotation, lighting, exponentiation, vector normalization, and perspective division (which are some of the most important data-intensive 3D graphics kernels) and propose a scheme to implement them on the CORDIC-augmented Sandbridge processor. Preliminary results indicate that the performance improvement within the extended instruction set ranges from 3× to 10× (with the exception of rigid body rotation).

show abstract

“…With T 3 , all threads can be simultaneously executing instructions, but only one thread may issue an instruction on a cycle boundary [14]. This constraint is also imposed on round-robin threading.…”

Section: Sandblaster Processormentioning

confidence: 99%

“…The Sandblaster Processor utilizes a unique combination of techniques including hardware support for multiple threads, compound instructions, SIMD vector operations, and instruction set support for Java code [14]. The Sandblaster Processor provides substantial parallelism and throughput for high-performance SDR, while maintaining fast interrupt response, high-level language programmability, and low power dissipation.…”

Section: Sandblaster Processormentioning

confidence: 99%

“…Sandbridge technologies has developed the SB3010, a SDR baseband processor that performs physical layer processing in software for a variety of communication systems including 2Mbps WCDMA, 11Mbps IEEE802.11b, GSM/GPRS, and GPS [14]. The SB3010 consists of four multithreaded Sandblaster Processor cores, an ARM9 applications processor, on-chip instruction caches and data memories, a programmable RF interface, and several peripheral interfaces.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Instruction set extensions for software defined radio on a multithreaded processor

Mamidi

Blem

Schulte

et al. 2005

Proceedings of the 2005 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

Self Cite

View full text Add to dashboard Cite

Software defined radios, which provide a programmable solution for implementing the physical layer processing of multiple communication standards, are widely recognized as one of the most important new technologies for wireless communication systems. Emerging communication standards, however, require tremendous processing capabilities to perform high-bandwidth physical-layer processing in real time.In this paper, we present instruction set extensions for several important communication algorithms including convolutional encoding, Viterbi decoding, turbo decoding, and Reed-Solomon encoding and decoding. The performance benefits of these extensions are evaluated using a supercomputer class vectorizing compiler and the Sandblaster lowpower multithreaded processor for software defined radio. The proposed instruction set extensions provide significant performance improvements, while maintaining a high degree of programmability.

show abstract

A Low-Power Multithreaded Processor for Baseband Communication Systems

Cited by 13 publications

References 8 publications

Software-Defined Radio Demonstrators: An Example and Future Trends

Software-Defined Radio Demonstrators: An Example and Future Trends

Software-based geometry operations for 3D computer graphics

Instruction set extensions for software defined radio on a multithreaded processor

Contact Info

Product

Resources

About