A low power and reduced area carry select adder

Rawat, Kuldeep; Darwish, T.; Bayoumi, Magdy

doi:10.1109/mwscas.2002.1187259

Cited by 33 publications

(8 citation statements)

References 5 publications

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“…The simulation parameters are given in Table 7. For measuring propagation delay we need to set the inputs such that the carry propagates from LSB to MSB [22]. We set A 31-0 = 1 and BB 31-0 = 0 to measure the worst-case delay.…”

Section: Simulation Parametersmentioning

confidence: 99%

Performance analysis of radix-4 adders

Asif

Vesterbacka

2012

Integration

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Abstract-We present a radix-4 static CMOS full adder circuit that reduces the propagation delay, PDP, and EDP in carrybased adders compared with using a standard radix-2 full adder solution. The improvements are obtained by employing carry look-ahead technique at the transistor level. Spice simulations using 45 nm CMOS technology parameters with a power supply voltage of 1.1 V indicate that the radix-4 circuit is 24% faster than a 2-bit radix-2 ripple carry adder with slightly larger transistor count, whereas the power consumption is almost the same. A second scheme for radix-2 and radix-4 adders that have a reduced number of transistors in the carry path is also investigated. Simulation results also confirm that the radix-4 adder gives better performance as compared to a standard 2-bit CLA. 32-bit ripple carry, 2-stage carry select, variable size carry select, and carry skip adders are implemented with the different full adders as building blocks. There are PDP savings, with one exception, for the 32-bit adders in the range 8% to 18% and EDP savings in the range 21% to 53% using radix-4 as compared to radix-2.

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Section: Simulation Parametersmentioning

confidence: 99%

Performance analysis of radix-4 adders

Asif

Vesterbacka

2012

Integration

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“…The literature gives a variety of solutions for optimizing adders using different techniques such as carry-select adders [11][12][13], carry save adders [14], carry lookahead adders [15][16][17][18], hybrid between carry-select and carry-lookahead adders [19][20][21][22][23][24], carry skip [25,26], and conditional-sum adders [27,28].…”

Section: Introductionmentioning

confidence: 99%

Optimized structures of hybrid ripple carry and hierarchical carry lookahead adders

Ibrahim

Gebali

2015

Microelectronics Journal

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“…Depending upon the area, delay, and power consumption, the various adders are categorized as ripple carry adder (RCA), carry select adder (CSLA), and carry lookahead adder (CLAA). CSLA provides a compromise between the large area with small delay of CLAA and small area but longer delay of RCA [8]. CSLA uses pair of RCAs for addition, that is, one block of RCA with in (carry in) = 0 and other block of RCA with in = 1.…”

Section: Introductionmentioning

confidence: 99%

Design of Low Power and Efficient Carry Select Adder Using 3-T XOR Gate

Singh¹,

Goel²

2014

Advances in Electronics

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In digital systems, mostly adder lies in the critical path that affects the overall performance of the system. To perform fast addition operation at low cost, carry select adder (CSLA) is the most suitable among conventional adder structures. In this paper, a 3-T XOR gate is used to design an 8-bit CSLA as XOR gates are the essential blocks in designing higher bit adders. The proposed CSLA has reduced transistor count and has lesser power consumption as well as power-delay product (PDP) as compared to regular CSLA and modified CSLA.

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A low power and reduced area carry select adder

Cited by 33 publications

References 5 publications

Performance analysis of radix-4 adders

Performance analysis of radix-4 adders

Optimized structures of hybrid ripple carry and hierarchical carry lookahead adders

Design of Low Power and Efficient Carry Select Adder Using 3-T XOR Gate

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