A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture

Mehta, Gayatri; Hoare, Raymond R.; Stander, Justin; Jones, Alex K.

doi:10.1109/fccm.2006.9

Cited by 2 publications

(7 citation statements)

References 5 publications

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“…We also targeted 5:1, 3553:1 and 355:1 multiplexer-based interconnects as described in Section 3. A detailed study of varying other parameters of the fabric such as the bit-width the ALUs can be found in [13]. Table 1 provides a summary of the area requirements of the benchmarks mapped to the fabric using the different multiplexing cardinalities and using the previously mentioned mapping strategies.…”

Section: Resultsmentioning

confidence: 99%

“…The energy required by the optimized fabric is within about 5-10X of an ASIC implementation and is 10X better than a Xilinx Virtex II Pro FPGA and 100X better than an Intel XScale processor operating at 733 MHz. A more detailed discussion of the tradeoffs of the reconfigurable fabric versus the ASIC, FPGA and embedded processor implementations can be found in [13].…”

Section: Fabric Technology Comparisonmentioning

confidence: 99%

“…Based on our initial design space exploration studies, a 4:1 interconnect was selected to create enough flexibility in the routing while reducing power consumption and delay in the fabric [12,13]. An example of this interconnection is shown in Figure 3.…”

Section: Benchmark Driven Interconnectmentioning

confidence: 99%

“…In previous work, the fabric architecture was developed based on multi-bit functional units and multi-bit routing structures configured through multiplexers [13]. As part of the previous work, an architectural design space exploration was completed that determined parameters for the functional units and routing.…”

Section: Introductionmentioning

confidence: 99%

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Interconnect Customization for a Coarse-grained Reconfigurable Fabric

Mehta

Slander

Baz

et al. 2007

2007 IEEE International Parallel and Distributed Processing Symposium

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This paper describes several system-level interconnection strategies for a coarse-grained reconfigurable fabric designed for low-energy hardware acceleration. A small, representative sub-graph for signal and image processing applications is used to predict the success of mapping larger applications onto the fabric device with these different interconnection strategies, which include 32:1, 8:1, 5:1, 4:1, 3553:1 (3:1, 5:1, 5:1, 3:1) and 355:1 (3:1, 5:1, 5:1) cardinalities. Three mapping techniques are presented and used to complete mappings onto several of these fabric instances including a mixed integer linear programming technique, a constraint programming approach, and a greedy heuristic. We present results for area (in number of required rows), power, delay, and energy as well as run times for mapping a set of signal and image processing benchmarks onto each of these interconnects. Our results indicate that the 5:1 interconnect provides the best overall results and does not require any additional hardware resources than the baseline 4:1 technique. When compared with other implementation strategies, the reconfigurable fabric energy consumption, using 5:1-based interconnect, is within 5-10X of a direct ASIC implementation, is 10X better than an Virtex II Pro FPGA and is 100X better than an Intel XScale processor.

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Section: Resultsmentioning

confidence: 99%

Section: Fabric Technology Comparisonmentioning

confidence: 99%

Section: Benchmark Driven Interconnectmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Interconnect Customization for a Coarse-grained Reconfigurable Fabric

Mehta

Slander

Baz

et al. 2007

2007 IEEE International Parallel and Distributed Processing Symposium

Self Cite

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“…Stripe-based fabrics in particular (e.g., see Figure 2) are quite promising due to their good fit to a data flow graph structure [5,25,8,9]. When a data flow graph is mapped to a stripe-style structure, however, data dependency edges often traverse multiple rows.…”

Section: Introductionmentioning

confidence: 99%

A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric

Yadav

Stander

Jones

et al. 2013

VLSICS

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Coarse-grained reconfigurable fabrics (CGRF's) have great promise for achieving low-energy flexible designs for an application domain. However a universally accepted architecture for coarse-grained reconfigurable fabrics has not yet crystallized, and many architectural options are still un-der consideration by the research and industry community. One scientific question is how to efficiently route inputs through a CGRF. This paper addresses this question in part by exploring various alternative input solu-tions for a stripe-based fabric. Alternative architectural styles examined in this paper include (i) integrated constants (IC) approach where constants are loaded in the registers local to the functional units; (ii) inputs coming from the side (ICS) where both constants and variable inputs can be routed to the stripe directly where needed; (iii) ICS with extended vertical interconnect (ICS-EV); and (iv) a combination of dedicated pass gates (DPs) with standard, IC, ICS, and ICS-EV architecture styles.We implemented these architecture styles using 90 nm ASIC process from Synopsys. We perform a detailed area and energy analysis on these architectures and present quantitative results in this paper. We observed that the fabric with ICS and 50% DPs is the best among these options, providing 31% energy savings and 62% area savings over a baseline architecture for our benchmark set.

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A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture

Cited by 2 publications

References 5 publications

Interconnect Customization for a Coarse-grained Reconfigurable Fabric

Interconnect Customization for a Coarse-grained Reconfigurable Fabric

A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric

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