DOI: 10.1109/date.2004.1268856
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Abstract: This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. The technique combines standard building blocks to make 'new' compound standard cells, which have a close to constant power consumption. Experimental results indicate a 50 times reduction in the power consumption fluctuations. 6 Automated design flow A major advantage of our proposed logic style is that it…

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