“…However, it is well known that the attenuation constant of the on-chip transmission line increases as the operating frequency increases due to losses in the conductive silicon substrate as well as the series resistance of the metallization. Various methods, such as high-resistivity silicon [2], front/back side micromachining [3], porous silicon [4], and proton implantation [5], have been reported to reduce the substrate loss. Nevertheless, most of the proposed methods are very difficult, if not impossible, to be integrated into the standard CMOS technology because of their inherent nonstandard processing steps.…”