A high performance gate engineered charge plasma based tunnel field effect transistor

Bashir, Faisal; Loan, Sajad A.; Rafat, M.; Alamoud, Abdul Rehman; Abbasi, Shuja A.

doi:10.1007/s10825-015-0665-5

Cited by 55 publications

(21 citation statements)

References 36 publications

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“…The boundary conditions set for region R1 considers band‐to‐band tunnelling, where the same is not regarded in R2. The dual‐metal DG TFET structure that exhibits high dc performance has been proposed earlier [18, 19]. To get accuracy, our simulation result is calibrated with the reported data for dual‐metal DG TFET [18].…”

Section: Resultsmentioning

confidence: 99%

“…The dual‐metal DG TFET structure that exhibits high dc performance has been proposed earlier [18, 19]. To get accuracy, our simulation result is calibrated with the reported data for dual‐metal DG TFET [18]. For better comparison, the total gate length of DG TFET is kept 50 nm, which is the same as considered in the reported works [18, 20–22].…”

Section: Resultsmentioning

confidence: 99%

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Evanescent mode based compact modelling of a dual‐metal double‐gate tunnel field‐effect transistor

Bose

Roy

2020

IET Circuits, Devices & Systems

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Evanescent mode based compact modelling of a dual‐metal double‐gate tunnel field‐effect transistor

Bose

Roy

2020

IET Circuits, Devices & Systems

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“…Although TFETs have various benefits, there are still some problems to be solved, such as the ambipolar behavior [6,7], low ON-state current (I ON ) [8], and less-than-idea SS. To solve these problems, different techniques such as the use of high-k dielectric materials [9], heterojunction engineering [10,11,12,13], source pocket based devices [14,15], junction-less concept based devices [16,17,18], and narrow bandgap materials have been investigated to boost I ON . Drain doping profile investigation [7], gate-drain electrode gap control [19], the hetero-dielectric box concept [20], and heterojunction engineering have been developed to restrain ambipolar behavior.…”

Section: Introductionmentioning

confidence: 99%

High Performance Drain Engineered InGaN Heterostructure Tunnel Field Effect Transistor

Duan¹,

Zhang²,

Chen³

et al. 2019

Micromachines

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A drain engineered InGaN heterostructure tunnel field effect transistor (TFET) is proposed and investigated by Silvaco Atlas simulation. This structure uses an additional metal on the drain region to modulate the energy band near the drain/channel interface in the drain regions, and increase the tunneling barrier for the flow of holes from the conduction band of the drain to the valence band of the channel region under negative gate bias for n-TFET, which induces the ambipolar current being reduced from 1.93 × 10−8 to 1.46 × 10−11 A/μm. In addition, polar InGaN heterostructure TFET having a polarization effect can adjust the energy band structure and achieve steep interband tunneling. The average subthreshold swing of the polar drain engineered heterostructure TFET (DE-HTFET) is reduced by 53.3% compared to that of the nonpolar DE-HTFET. Furthermore, ION increases 100% from 137 mA/mm of nonpolar DE-HTFET to 274 mA/mm of polar DE-HTFET.

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“…JLTFETs also include inferior I on and ambipolar behavior. To overcome these problems, different methods have been investigated, such as: using heterostructures at source/channel interfaces [37][38][39][40][41], the assumption of gate workfunction engineering [42][43][44][45], the adoption of hetero-gate dielectrics [46][47][48][49], using Gaussian-doping profiles [22,50,51], applying source pockets [52], the consideration of strain engineering [53,54], using ferroelectric insulators [40], and drain workfunction engineering for DLTFET [55,56].…”

Section: Introductionmentioning

confidence: 99%

Representation of heterostructure electrically doped nanoscale tunnel FET with Gaussian-doping profile for high-performance low-power applications

2018

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In this paper, a gallium antimonide junctionless tunnel field-effect transistor based on electrically doped concept (GaSb-EDTFET) is studied and simulated. The performance of the device is analyzed based on the energy band diagram and electric field profile. The on-current, transconductance, and cutoff frequency are enhanced in case of GaSb-EDTFET compared with Si-EDTFET due to the combination of the high tunneling efficiency of the narrow bandgap and the high-electron mobility of GaSb. On the other hand, the Gaussian-doping profile decreases the ambipolar and off current by increasing the tunneling barrier length at the drain/channel interface. Hence, applying Gaussian-doping profile on GaSb-EDTFET makes it a suitable candidate for analog and digital applications. Next, heterostructure channel/source interface EDTFET is studied which uses GaSb for the source and AlGaSb for the drain and channel regions. Then, it has been optimized by numerical simulation in terms of aluminum (Al) composition. The optimal Al composition was founded to be around 10% (x = 0.1). It is shown that the blend of Gaussian-doping profile and the heterostructure channel/source interface with optimal Al composition remarkably reduces ambipolar current amount to a value of 1.3 × 10 −23 A/μm. The improvements in terms of I off , I on , I on /I off rate, subthreshold swing, transconductance, cutoff frequency, and also suppressed ambipolar behavior are illustrated by numerical simulations.

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A high performance gate engineered charge plasma based tunnel field effect transistor

Cited by 55 publications

References 36 publications

Evanescent mode based compact modelling of a dual‐metal double‐gate tunnel field‐effect transistor

Evanescent mode based compact modelling of a dual‐metal double‐gate tunnel field‐effect transistor

High Performance Drain Engineered InGaN Heterostructure Tunnel Field Effect Transistor

Representation of heterostructure electrically doped nanoscale tunnel FET with Gaussian-doping profile for high-performance low-power applications

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